臺灣博碩士論文加值系統

本論文主要分為四個主題，第一個主題為壓控振盪器的設計，第一個振盪器為使用gm-boosted技巧降低Colpitts震盪器的起振條件，並以低電壓操作達到低功率消耗，再使用四階的LC-Tank來增加輸出功率降低相位雜訊，電路以TSMC 0.18 um 製程完成晶片製作，量測操作頻率為15 GHz，相位雜訊在1MHz偏移量為-105.7dBc/Hz，消耗功率為2.1mW。第二個振盪器使用可變電容串聯電感的架構，共振電容的損耗改善相位雜訊，電路以TSMC 0.18 um 製程完成晶片製作，量測操作頻率為22.8 GHz，相位雜訊在1MHz偏移量為-111.76dBc/Hz，消耗功率為12.5mW。
第二個主題為注入鎖定除二除頻器的設計，第一個除頻器使用電阻串聯的架構，除了增加注入電晶體的轉導值，也可降低LC-tank的Q值，增加除頻範圍，電路以TSMC 0.18 um 製程完成晶片製作，量測輸入頻率為7 GHz至13 GHz，除頻比率為60%，消耗功率為17mW。第二個除頻器使用四階LC-Tank的架構，來增加鎖定範圍，並在訊號路徑上串聯電阻，增加注入電晶體轉導值與降低LC-tank的Q值，進一步提升鎖定範圍，電路以TSMC 0.18 um 製程完成晶片製作，量測輸入頻率為26.4 GHz至32.6 GHz，除頻比率為21%，消耗功率為12.5mW。第三個除頻器使用同相位雙注入技巧來提升注入訊號電流，增加鎖定範圍，並使用電流再利用的架構來降低功率消耗，電路以TSMC 0.18 um 製程完成晶片製作，量測輸入頻率為24.5 GHz至29 GHz，除頻比率為16.8%，消耗功率為1.26mW。
第三個主題為注入鎖定除三除頻器的設計，第一個除頻器由單平衡式的混波器與環型注入鎖定除二除頻器所構成，利用環型除頻器較小輸入功率仍能維持較大鎖定範圍的特點並以差動注入的方式輸入訊號提升除三除頻器的鎖定範圍，電路以TSMC 0.18 um 製程完成晶片製作，量測輸入頻率為56 GHz至57 GHz，消耗功率為14.8mW。第二個除頻器在混波器與除二除頻器中加入放大器，使訊號從混波器輸出後放大，再進入除二除頻器，增加鎖定範圍，電路以TSMC 0.18 um 製程完成晶片製作，量測輸入頻率為17.2 GHz至21.9 GHz，消耗功率為24.4mW。
第四個主題為前端電路整合的設計，第一級使用疊接式共源極低雜訊放大器，提供高增益與低雜訊，第二級使用主動式分波器，提供增益並將單端訊號轉為差動訊號輸出至第三級，第三級混波器使用Current-beeling的技巧，來降低電流轉導級的閃爍雜訊，達到低雜訊的設計。

The thesis includes four topics. The first topic describes the voltage control oscillator(VCO). The first VCO uses gm-boosted technique to reduce the startup condition, and operate at low voltage for low power consumption. Using Fourth-order LC-Tank to increase the output power to lower the phase noise. The circuit operated at 15 GHz, phase noise -105.7dBc/Hz at 1MHz offset, power consumption is 2.1mW, using TSMC 0.18 um technology to fabricate the chip.The second VCO use admittance transforming technique to improve the phase noise. The circuit operated at 22.8 GHz, phase noise -111.76 dBc/Hz at 1MHz offset, power consumption is 12.5 mW, using TSMC 0.18 um technology to fabricate the chip.
The second topic describes the 2:1 injection-locked frequency dividers(ILFD). The first ILFD implement the topology, which used series resistance to increase the injection transistors’ transconductor and decrease quality factor of LC-tank for wide locking range. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 7 GHz to 13 GHz, the locking range ratio is 60%, power consumption is 17 mW. The second ILFD uses Fourth-order LC-Tank network to increase locking range. Also implement the series resistance to increase the injection transistors’ transconductor and decrease quality factor of LC-tank for wider locking range. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 26.4 GHz to 32.6 GHz, the locking range ratio is 21%, power consumption is 12.5 mW. The third ILFD use double injection technique to increase locking range and a current re-used architecture to decrease power consumption. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 24.5 GHz to 29 GHz, the locking range ratio is 16.8 %, power consumption is 1.26 mW.
The third topic describes the 3:1 injection-locked frequency dividers. The first one adopts a mixer and a 2:1 injection-locked frequency divider. By using the ring divider which can be maintained in a larger locking range at small input power. The differential input signal can enhance the locking range of 3:1 divider. The chip implementation used TSMC 90 nm technology, the measured input frequency is 56 GHz to 57 GHz, power consumption is 14.8 mW. The second one enhance the locking range by using an amplifier to magnify the output signal from mixer. The chip implementation used TSMC 0.18 um technology, the measured input frequency is 17.2 GHz to 21.9 GHz, power consumption is 24.4 mW.
The last topic is the design of the reciver. The first stage is a cascade common gate low noise amplifier(LNA),which offer high gain and low noise. The second stage is an active balun, which provide gain and divide the single-end signal to differential signal. The third stage a mixer, which used Current-beeling technique to improve the flicker noise.

誌謝 I
摘要(中文) II
摘要(英文) III
目錄 V
圖目錄 VII
表目錄 XIII

第一章 序論
1-1 研究動機 1
1-2 文獻回顧 6

第二章 壓控振盪器
2-1 振盪器 8
2-2低功耗Colpitts壓控振盪器 10
2-2-1 電路架構 10
2-2-2 模擬和量測結果 19
2-2-3 電路佈局圖 22
2-2-4 結果討論 24
2-3分散式LC-Tank壓控震盪器 26
2-3-1 電路架構 26
2-3-2 模擬和量測結果 32
2-3-3 電路佈局圖 35
2-3-4 結果討論 37

第三章 注入鎖定除二除頻器
3-1 注入鎖定除二除頻器 38
3-2使用串聯MOS電阻之注入鎖定除二除頻器 40
3-2-1 電路架構 40
3-2-2 模擬和量測結果 46
3-2-3 電路佈局圖 51
3-2-4 結果討論 52
3-3寬頻注入鎖定除二除頻器 53
3-3-1 電路架構 53
3-3-2 模擬和量測結果 60
3-3-3 電路佈局圖 66
3-3-4 結果討論 67
3-4低功耗雙注入鎖定除二除頻器 68
3-4-1 電路架構 68
3-4-2 模擬和量測結果 75
3-4-3 電路佈局圖 81
3-4-4 結果討論 82

第四章 注入鎖定除三除頻器
4-1 注入鎖定除三除頻器 83
4-2 V-Band注入鎖定除三除頻器 85
4-2-1 電路架構 85
4-2-2 模擬和量測結果 93
4-2-3 電路佈局圖 99
4-2-4 結果討論 100
4-3使用Gm-Boosted技巧之環型注入鎖定除三除頻器 101
4-3-1 電路架構 101
4-3-2 模擬和量測結果 105
4-3-3 電路佈局圖 111
4-3-4 結果討論 112

第五章 射頻前端電路整合
5-1 系統架構 113
5-2低雜訊放大器 114
5-3主動Balun 117
5-4混波器 120
5-5低雜訊前端電路 125
5-6模擬和量測結果 126
5-7電路佈局圖 135
5-8結果討論 136

第六章 總結與未來工作 138

參考文獻 140

[1] Behzad Razavi,”Design of analog CMOS integrated circuits”, McGraw Hill,2001.
[2] David M.Pozar,”Microwave engineering “, John Wiley&Sons,Inc.
[3] Behzad Razavi, “RF Microelectronics”, Prentice-Hall,1998.
[4] Ahmad Mirzaei, Mohammad E. Heidari, Rahim Bagheri, Saeed Chehrazi, and Asad A. Abidi,” The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking”, IEEE Journal of Solid-State Circuits, pp.1916-1932, September 2007.
[5] Behzad Razavi” A Study of Injection Locking and Pulling in Oscillators”, IEEE Journal of Solid-State Circuits, pp.1415-1424, September 2004.
[6] Chien-Feng Lee, Sheng-Lyang Jang, and M.-H. Juang, “A Wide Locking Range Differential Colpitts Injection Locked Frequency Divider”, IEEE Microwave and Wireless Components Letters , pp.790-792, November 2007.
[7] Marc Tiebout, “A CMOS Direct Injection-Locked Oscillator Topology as High-Frequency Low-Power Frequency Divider”, IEEE Journal of Solid-State Circuits, pp.1170-1174, July 2004.
[8] Sheng-Lyang Jang, Jhong-Chen Luo, Chia-Wei Chang, Chien-Feng Lee, and
Jhin-Fang Huang,” LC-Tank Colpitts Injection-Locked Frequency Divider With Even and Odd Modulo”, IEEE Microwave and Wireless Components Letters , pp.113-115, February 2009.
[9] S.-L. Jang, Ming-Hsiang Suchen, and Chien-Feng Lee,” Colpitts Injection-Locked Frequency DividerImplemented With a 3-D Helical Transformer”, IEEE Microwave and Wireless Components Letters, pp.410-412, June 2008.
[10] Jri Lee, and Behzad Razavi,” A 40-GHz Frequency Divider in 0.18-um CMOS Technology”, IEEE Journal of Solid-State Circuits, pp.594-601, April 2004.
[11] Sujiang Rong, Alan W.L. Ng, Howard C. Luong,” 0.9mW 7GHz and 1.6mW 60GHz Frequency Dividers with Locking-Range Enhancement in 0.13um CMOS”, IEEE ISSCC, pp.96-97, February 2009.
[12] Jun-Chau Chien, Liang-Hung Lu,“ 40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18um CMOS“, IEEE ISSCC, pp.544–545, February 2007.
[13] Pierre Mayr,Christopher Weyers,Ulrich Langmann,"A 90GHz 65nm CMOS
Injection-Locked Frequency Divider", IEEE ISSCC, pp.198-596, Feburary 2007.
[14] Behzad Razavi,” A Millimeter-Wave Circuit Technique”, IEEE Journal of Solid-State Circuits, pp.2090-2098, September 2008.
[15] Jun-Chau Chien, and Liang-Hung Lu,“ Analysis and Design of Wideband Injection-Locked Ring Oscillators With Multiple-Input Injection“, IEEE Journal of Solid-State Circuits, pp.1906-1915, September 2007.
[16] Chung-Chun Chen,Hen-Wai Tsao,and Huei Wang,”Design and Analysis of
CMOS Frequency Dividers With Wide Input Locking Ranges“, IEEE
Transactions on Microwave Theory and Techniques, pp.3060-3069,
December 2009.
[17] U. Singh and M. Green, “High-frequency CML clock dividers in 0.13-um CMOS operating up to 38 GHz”, IEEE Journal of Solid-State Circuits, pp.1658-1661, August 2005.
[18] Chung-Yu Wu, and Chi-Yao Yu,” Design and Analysis of a Millimeter-Wave Direct Injection-Locked Frequency Divider With Large Frequency Locking Range”, IEEE Transactions on Microwave Theory and Techniques, pp.1649-1658, August 2007.
[19] Lan-Chou Cho,Kun-Hung Tsai,Chao-Ching Hung,Shen-Iuan Liu,"93.5~
109.4GHz CMOS Injection-locked Frequency Divider with 15.3% locking
range", IEEE VLSI Circuit Symposium, pp.86-87, June 2008.
[20] Lan-Chou Cho, Kun-Hung Tsai,C.-C.Hung,Shen-Iuan Liu,"81.5-85.9 GHz
injection-locked frequency divider in 65nm CMOS", IEEE Electronics
Letters, pp.966-986, July 2008.
[21] Kun-Hung Tsai, Lan-Chou Cho,Jia-Hao Wu,Shen-Iuan Liu,"3.5mW W-Band
Frequency Divider with Wide Locking Range in 90nm CMOS Technology",
IEEE ISSCC, pp.466-628,February 2008.
[22] I-Ting Lee,Kun-Hung Tsai,and Shen-Iuan Liu, "A 104-to-112.8-GHz CMOS
Injection-Locked Frequency Divider", IEEE Transactions on Circuits and Systems—II: Express Briefs, pp.555-559, July 2009.
[23] Luo, T.N., Bai, S.Y., and Chen, Y.-J.E., ”A 60-GHz 0.13-um CMOS divide-by-three frequency divider”, IEEE Transactions on Microwave Theory and Techniques, pp. 2409–2415, November 2008.
[24] J T.-N. Luo, S.-Y. Bai and Y.-J.E. Chen,” 77 GHz CMOS injection-locked Miller frequency divider”, IEEE Electronics Letters, pp.57-59, January 2009.
[25] S.-L. Jang, J.-C. Luo, C.-W. Chang, C.-F. Lee, and J.-F. Huang, “LCtank Colpitts injection-locked frequency divider with even and odd modulo,” IEEE Microw. Wireless Component Letter, pp.113-115, February 2009.
[26] Wang, C.H., Chen, C.-C., Lei, M.-F., Chuang, M.-C., and Wang, H.”A 66-72 GHz divide-by-3 injection-locked frequency divider in 0.13 um CMOS technology”, IEEE Asian Solid-State Circuits Conference, pp. 344–347, November 2007.
[27] Jun-Chau Chien, and Liang-Hung Lu, Wu, H., and Zhang, L.,”A 16- to-18 GHz
0.18um Epi-CMOS divideby-3 injection-locked frequency divider”, IEEE
ISSCC, pp. 2482–2491, February 2006
[28] J. C. Rudell, J.-J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon,and P. R. Gray, “A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications”, IEEE Journal of Solid-State Circuits, pp. 2071–2088, December 1997.
[29] Chin-Lung Yang and Yi-Chyun Chiang,” Low Phase-Noise and Low-Power CMOS VCO Constructed in Current-Reused Configuration”, IEEE Microwave and Wireless Components Letters , pp.136-138, February 2008.
[30] S. Lo and S. Hong, “Noise property of a quadrature balanced VCO,” IEEE Microwave and Wireless Components Letters, pp.673–675, October 2005.
[31] M. D. Wei, S. F. Chang, and Y. J. Yang, “A CMOS backgate-coupled QVCO based on back-to-back series varactor configuration for minimal AM-to-PM noise conversion,” IEEE Microw. Wireless Component Letter, pp. 320–322, May 2009.
[32] C. C. Li, T. P. Wang, C. C. Kuo, M. C. Chuang, and H. Wang, “A 21 GHz complementary transformer coupled CMOS VCO,” IEEE Microwave Wireless Compon. Letter, pp. 278–280, April 2008.
[33] Donhee Ham,Ali Hajimiri,"Concepts and Methods in Optimization of Integrated
LC VCOs", IEEE Journal of Solid-State Circuits, pp.896-909, June 2001.
[34] Xiaoyong Li, Sudip Shekhar, and David J. Allstot,” Gm-Boosted Common-Gate LNA and Differential Colpitts VCO/QVCO in 0.18-um CMOS”, IEEE Journal of Solid-State Circuits, pp.2609-2619, December 2005.
[35] Jong-Phil Hong, and Sang-Gug Lee,” Low Phase Noise Gm-Boosted Differential Gate-to-Source Feedback Colpitts CMOS VCO”, IEEE Journal of Solid-State Circuits, pp.3079-3091, November 2009.
[36] Emad Hegazi,Henrik Sjöland,and Asad A. Abidi,” A Filtering Technique to Lower LC OscillatorPhase Noise”, IEEE Journal of Solid-State Circuits, pp.1649-1652, December 2001.
[37] Ping-Chen Huang, Ming-Da Tsai,George D. Vendelin, Life,Huei Wang, Chun-Hung Chen, and Chih-Sheng Chang,” A Low-Power 114-GHz Push–Push CMOS VCO Using LC Source Degeneration”, IEEE Journal of Solid-State Circuits, pp.1230-1239, June 2007 .
[38] Guochi Huang, and Byung-Sung Kim,” Low Phase Noise Self-Switched Biasing
CMOS LC Quadrature VCO”, IEEE Transactions on Microwave Theory and Techniques, pp.344-351, February 2009.
[39] C.K. Liang and B. Razavi, “Systematic Transistor and Inductor Modeling for
Millimeter-Wave Design", IEEE Journal of Solid-State Circuits, pp.450-457, February 2009.
[40]Hsieh-Hung Hsieh, and Liang-Hung Lu," A V-Band CMOS VCO With an
Admittance-Transforming Cross-Coupled Pair", IEEE Journal of Solid-State Circuits, pp.1689-1696, June 2009.
[41] Seung Wan Chai, Jaemo Yang, Bon-Hyun Ku, and Songcheol Hong,” Millimeter Wave CMOS VCO with a High Impedance LC tank”, IEEE Radio Frequency Intergrated Circuits Symposium, pp.545-548, May 2010.
[42] Jinsung ParkE, Chang-Ho LeeE, Byung-Sung Kim and Joy Laskar,” Design and Analysis of Low Flicker-Noise CMOS Mixers for Direct-Conversion Receivers”, IEEE Transactions on Microwave Theory and Techniques, pp.4372-4380, December 2006.
[43] M. T. Terrovits and R. G. Meyer, “Noise in current-commutating CMOS mixers”, IEEE Journal of Solid-State Circuits, pp.772–783, June 1999.
[44] Derek K. Shaeffer,and Thomas H. Lee,” A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier”, IEEE Journal of Solid-State Circuits, pp.32-33, May 1997
[45] Jri Lee,Ming-Shuan Chen, and Huai-De Wang,” Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data” ,IEEE Journal of Solid-State Circuits, pp.2120-2133, September 2008.
[46] R. Svitek and S. Raman, “5–6 GHz SiGe active I/Q subharmonic mixers with power supply noise effect characterization”, IEEE Microwave and Wireless Components Letters, pp. 319–321, July 2004.
[47] Hsiao-Chin Chen, Tao Wang, and Shey-Shi Lu, “A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler”, IEEE Journal of Solid-State Circuits, pp.1963-1975, September 2007.
[48] Thomas H. Lee,Hirad Samavati, and Hamid R. Rategh, “5-GHz CMOS Wireless LANs”, IEEE Transactions on Microwave Theory and Techniques, pp.268-280, January 2002.
[49] Sining Zhou,and Mau-Chung Frank Chang,” A CMOS Passive Mixer With Low Flicker Noise for Low-Power Direct-Conversion Receiver”, IEEE Journal of Solid-State Circuits, pp.1084-1093, May 2005.
[50] Chun-Cheng Wang,Zhiming Chen,Vipul Jain,Payam Heydrai, "Design and
Analysis of a Silicon-Based Millimeter-Wave Divide-by-3 Injection-Locked
Frequency Divider", IEEE Silicon Monolithic Integrated Circuits in RF
Systems, pp.1-4, January 2009.
[51] Hui Wu, and Lin Zhang, “A 16-to-18GHz 0.18-m Epi-CMOS Divide-by-3
Injection-Locked Frequency Divider“, IEEE Conferences of Solid-State
Circuits, pp.2482-2491, February 2006.
[52] Sheng-Lyang Jang, Chien-Feng Lee, and Wei-Hsung Yen, “A Divide-by-3
Injection Locked Frequency Divider With Single-Ended Input”, IEEE
Microwave and Wireless Components Letters, pp.142-144, February 2008.
[53] Dong Ho Lee, Jeonghu Han, Changkun Park,and Songcheol Hong,“A CMOS
Active Balun Using Bond Wire Inductors and a Gain Boosting Technique”, IEEE Microwave and Wireless Components Letters, pp.676-678, September 2007.
[54] Tzung-Han Wu, and Chinchun Meng,” 5.2/5.7-GHz 48-dB Image Rejection GaInP/GaAsHBT Weaver Down-Converter Using LO Frequency Quadrupler”, IEEE Journal of Solid-State Circuits, pp.2468-2480, November 2006.
[55] Chong-Ru Wu, Hsieh-Hung Hsieh, Li-Shin Lai, and Liang-Hung Lu, “ A 3–5 GHz Frequency-Tunable Receiver Frontend for Multiband Applications“, IEEE
Microwave and Wireless Components Letters, pp.638-640, September 2008.
[56] Ahmed Amer, Emad Hegazi,and Hani F. Ragaie,” A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation”, IEEE Journal of Solid-State Circuits, pp.323-328, February 2007.
[57] Stephan C. Blaakmeer, Eric A. M. Klumperink, Domine M. W. Leenaerts, and Bram Nauta,” The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology”, IEEE Journal of Solid-State Circuits, pp.2706-2715, December 2008.
[58] Kuang-Wei Cheng, Karthik Natarajan, and David J. Allstot,” A Current Reuse Quadrature GPS Receiver in 0.13 um CMOS”, IEEE Journal of Solid-State Circuits, pp.510-523, March 2010.
[59] D. B. Leeson, “A simple model of feedback oscillator noise spectrum”, IEEE Proceedings , pp.329-330, February 1966.
[60] Lianming Li, Patrick Reynaert, and Michiel S. J. Steyaert,” Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank”, IEEE Journal of Solid-State Circuits, pp.1950-1958, July 2009.
[61] Hsieh-Hung Hsieh, Yu-Hsin Chen, and Liang-Hung Lu,“ A Millimeter-Wave CMOS LC-Tank VCO With an Admittance-Transforming Technique“, IEEE Transactions on Microwave Theory and Techniques, pp.1854-1861, September 2007.
[62] Tang-Nian Luo, and Yi-Jan Emery Chen, ”A 0.8-mW 55-GHz Dual-Injection-Locked CMOS Frequency Divider”, IEEE Transactions on Microwave Theory and Techniques, pp.620-625, March 2008.
[63] Andrea Mazzanti, Paola Uggetti, and Francesco Svelto, ”Analysis and Design of Injection-Locked LC Dividers for Quadrature Generation”, IEEE Journal of Solid-State Circuits, pp.1425-1433, September 2004.
[64] Hsieh-Hung Hsieh, and Liang-Hung Lu, “A Low-Phase-Noise K-Band CMOS VCO“, IEEE Microwave and Wireless Components Letters, pp.552-554, October 2006.
[65] To-Po Wang,” A K-Band Low-Power Colpitts VCO With Voltage-to-Current Positive-Feedback Network in 0.18 um CMOS”, IEEE Microwave and Wireless Components Letters, pp.218-220, April 2011.
[66] Szu-Ling Liu, Kuan-Han Chen, Tsu Chang, and Albert Chin,” A Low-Power K-Band CMOS VCO With Four-Coil Transformer Feedback”, IEEE Microwave and Wireless Components Letters, pp.459-461, August 2010.
[67] Jaemo Yang, Choul-Young Kim, Dong-Wook Kim, and Songcheol Hong,” Design of a 24-GHz CMOS VCO With an Asymmetric-Width Transformer”, IEEE Transactions on Circuits and Systems—II: Express Briefs, pp.173-177, March 2010.
[68] Hsien-Ku Chen, Da-Chiang Chang, Ying-Zong Juang, and Shey-Shi Lu, ”A 30-GHz Wideband Low-Power CMOS Injection-Locked Frequency Divider for 60-GHz Wireless-LAN”, IEEE Microwave and Wireless Components Letters, pp.145-147, February 2008.
[69] Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, and Tadahiro Kuroda,”20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range”, IEEE Journal of Solid-State Circuits, pp.610-618, March 2008.
[70]傅冠霖,”LC-Tank振盪器相位雜訊與消耗功率設計之權衡與寬頻注入鎖定除頻器,”國立中興大學電機工程學系碩士學位論文,Jan 2011.
[71]柯柏丞,”應用於雙頻帶系統之本地振盪訊號源電路設計,” 國立中興大學電機工程學系碩士學位論文,July 2010.
[72]陳奕辰,”使用雜訊消除技巧之雙頻帶無線區域網路射頻前端設計,”國立中興大學電機工程學系碩士學位論文,July 2010.
[73]陳臆聰”24-GHz CMOS壓控振盪器與24-及60-GHz除頻器之研製,”國立成功大學電腦與通信工程研究所碩士學位論文,July 2009.
[74]楊智文,”90奈米雙閘極疊接電晶體之射頻特性分析與其應用”國立中興大學電機工程學系碩士學位論文,July 2009.
[75]徐達道,”應用於超寬頻系統之低功率主動性相位分離器與混波器之設計”國立交通大學電子工程學系碩士學位論文, June 2006.