臺灣博碩士論文加值系統

在本論文中，使用了TSMC 0.18um CMOS與TSMC 0.35 SiGe先進製成來設計低雜訊放大器，其中有三顆晶片式用於UWB系統中，低雜訊放大器是接收機中一個關鍵電路，一個低雜訊放大器的性能好壞可從高增益、低雜訊、輸入與輸出反射係數、低功率損耗等電路參數去決定。在我的設計中，廣泛的使用回授架構來達成所要的增益平坦度與輸入匹配。尤其是在寬頻電路方面，輸入匹配上是非常困難的，且通常輸入端常會處於匹配和雜訊的取捨，雖然回授降低了增益，但在現今元件製程上，本質增益的提高可克服此問題。另外一個晶片電路是設計適用於24GHz的低雜訊放大器，藉由Common Gate Resister Feedback(CGRF)的方式可降低首級的雜訊，進而造成整體電路的低雜訊。
在第一顆晶片中，採用Folded架構去實現3-5GHz的低雜訊放大器，搭配兩組回授電路提高增益平坦度，晶片總面積為1.21 mm × 1.15 mm。
在第二顆晶片中，採用三級電路去實現24GHz頻段的低雜訊放大器，且對首級分析其雜訊，晶片總面積為1.08 mm × 0.96 mm。
在第三顆晶片中，使用了台積電的SiGe製程技術。除了使用傳統電流再使用式架構來實現低雜訊放大器，亦引入回授機制，以大大提升了增益的平坦度（Gain flatness），晶片總面積為1.26 mm × 1.18 mm。
在第四顆晶片中，使用傳統的Cascode電路，回授RC提供輸入匹配，藉由Body端偏壓，可提高轉導，進而抑制雜訊，晶片總面積為1.07 mm × 1.02 mm。

In this thesis，we employed the TSMC 0.18um CMOS processes and TSMC 0.35um SiGe processes to design and implement the low noise amplifiers. Among these amplifiers, three circuits are suitable for the applications of IEEE 802.15.3a ultra wide band standard. The low noise amplifier is a key component for the front end of receivers. Sufficient gain, low noise, good input and output matching, low power consumption are important performances of a low noise amplifier. The feedback topology is generally used in my design. By this way, gain flatness and input matching can be attained. Especially, the broadband matching is very difficult in the input terminal. Input impedance matching and noise matching are usually trade-off. Though feedback topology decreases the gain, but the intrinsic gain of modern active devices is enough to face the persecution. Another circuit is a 24GHz low noise amplifier, using the common gate topology as the input stage. By the Common Gate Resister Feedback (CGRF) skill, we can suppress noise of the first stage and then overall noise can be lower.
In the first chip, a folded-cascode 3-5GHz UWB LNA is designed with feedback technologies to enhance gain flatness. The area of the chip is 1.21 mm × 1.15 mm. In the second chip, a 24GHz LNA is implemented by using three-stage technology. In addition, noise contribution of the first stage is analyzed. The whole area of the chip is 1.08 mm × 0.96 mm. In the third chip, the TSMC 0.35um SiGe processes is used to implement a current-reused LNA. The feedback topology is added to attain the gain flatness. The whole area of the chip is 1.26 mm × 1.18 mm. In the fourth chip, the traditional cascode technology with feedback technology is used to attain the input matching. In addition, the body-biasing technology is used to enhance the MOS tranconductance. The area of the chip is 1.27 mm × 1.12 mm.

Contents
中文摘要------------------------------------------------------------------------------------- I
英文摘要----------------------------------------------------------------------------------- II
誌謝 ----------------------------------------------------------------------- III
Contents ---------------------------------------------------------------------- IV-VI
List of tables --------------------------------------------------------------------------- VII
List of Figures ----------------------------------------------------------------------- VIII-X
Chapter1緒論
1.1 簡介Ultra Wide Band (WUB)------------------------------------------------ 1
1.2 直接序列UWB --------------------------------------------------------------- 2
1.3 MB-OFDM UWB -------------------------------------------------------------- 3
Chapter2接收機架構
2.1系統簡介----------------------------------------------------------------------- 4
2.1.1 類比與數位系統------------------------------------------------------ 4
2.1.1.1類比系統---------------------------------------------------- 5
2.1.1..2數位系統----------------------------------------------------- 5
2.2 超外差式接收器 (Super-Heterodyne Receiver)----------------------------- 7
2.2.1 鏡像頻率 (Image) --------------------------------------------- 8
2.2.2 半中頻 (Half IF) -------------------------------------------- 9
2.3 直接降頻接收器 (Direct Conversion Receiver DCR)---------------------------- 10
2.3.1 直流準位偏移 (DC Offset) ---------------------------------------- 11
2.3.2 偶次諧波失真 (Even-Order Distortion) ----------------------------- 12
2.3.3 顫動雜訊(Flicker Noise) ------------------------------------------------ 13
2.4 接收機雜訊源 (Receiver Noise)--------------------------------------------- 13
2.4.1 接收機熱雜訊 (Receiver Thermal Noise)--------------------------- 13
2.4.2 發射端雜訊--------------------------------------------------------------- 15
2.4.3 本地振盪器雜訊與干擾 (LO Leakage and Interference)-------- 16
2.5 傳播效應 (Propagation Effects)-------------------------------------------------------- 17
2.5.1 路徑損耗(Path Loss)----------------------------------------------------- 17
2.5.2 多重路徑與通道衰減 (Multipath and Fading)--------------------- 18
2.5.3 等化器 (Equalization)、分集 (Diversity)、加密 (Coding)----- 19
Chapter3高頻電路設計考量
3.1 散射參數 (Scattering Factor；S parameter)------------------------ 20
3.2 增益 (Gain)------------------------------------------------------------- 23
3.3 穩定度 (Stability)---------------------------------------------------------- 26
3.4 非線性效應 (Effect of Nonlinearity)--------------------------------- 27
3.4.1 諧波項 (Harmonics)------------------------------------- 28
3.4.2 1dB增益壓縮點 (1dB Gain Compression Point)---- 29
3.4.3 交互調變與三階截斷點 (Intermodulation and Third-Orde
Intercept Point )---------------------------------------------- 30
3.4.4 IP3的計算-------------------------------------------------- 32
3.5阻抗匹配網路 (Impedance Matching Network )--------------------- 35
3.5.1 電阻匹配------------------------------------------------------- 38
3.5.2 電晶體主動匹配---------------------------------------------- 39
3.5.3 源極退化電感匹配------------------------------------------ 40
3.5.4 LC-Ladder匹配--------------------------------------------- 42
Chapter4雜訊分析
4.1 雜訊簡介------------------------------------------------------------------ 44
4.1.1 功率頻譜密度 (Power Spectral density；PSD)------ 44
4.1.2 白色頻譜 (White Spectrum)------------------------------- 45
4.1.3 相關與非相關雜訊源------------------------------------- 46
4.2 電阻熱雜訊------------------------------------------------------------- 47
4.3 MOS中的雜訊---------------------------------------------------------- 49
4.3.1 通道熱雜訊-------------------------------------------------- 49
4.3.2 閘極誘發雜訊----------------------------------------------- 49
4.3.3 MOSFET中的Flicker Noise---------------------------------- 51
4.4 Bipolar中的雜訊-------------------------------------------------------- 52
4.5 Bipolar雜訊最佳化----------------------------------------------------- 53
4.5.1 雜訊因子與雜訊參數-------------------------------------- 53
4.5.2 雜訊參數求法----------------------------------------------- 54
4.5.3 Bipolar 雜訊雙埠網路計算------------------------------- 56
4.6 雜訊最佳化的證明------------------------------------------------------ 59
4.7 CMOS雜訊最佳化及與Bipolar的比較----------------------------- 61
4.8 多級電路雜訊計算-------------------------------------------------------- 63
Chapter 5 電路實作-
5.1 設計流程--------------------------------------------------------------------- 65
5.2應用於超寬頻3-5GHz低供應電壓之低雜訊放大器-------------- 66
5.2.1電路架構---------------------------------------------------------- 66
5.2.2架構說明---------------------------------------------------------- 66
5.2.3模擬與量測------------------------------------------------------- 67
5.2.4規格列表---------------------------------------------------------- 72
5.3降低基板耦和效應用於24GHz之低雜訊放大器------------------ 73
5.3.1電路架構---------------------------------------------------------- 73
5.3.2架構說明---------------------------------------------------------- 73
5.3.3模擬與量測------------------------------------------------------- 80
5.3.4規格列表---------------------------------------------------------- 84
5.4應用於全頻帶電流再使用式之低雜訊放大器---------------------- 85
5.4.1電路架構---------------------------------------------------------- 85
5.4.2架構說明---------------------------------------------------------- 85
5.4.3模擬結果---------------------------------------------------------- 86
5.4.4規格列表---------------------------------------------------------- 90
5.5轉導增強式全頻帶低雜訊放大器-------------------------------------- 91
5.5.1電路架構---------------------------------------------------------- 91
5.5.2架構說明---------------------------------------------------------- 91
5.5.3模擬結果---------------------------------------------------------- 92
5.5.4規格列表---------------------------------------------------------- 96





List of tables
表5.1 3-5GHz低供應電壓之低雜訊放大器 ------------------------------------- 72
表5.2 24GHz低雜訊放大器 ------------------------------------------------------ 84
表5.3 電流再使用式低雜訊放大器三種不同Corner Case模擬之比較 -- 90
表5.4 Post-sim後三種不同Corner Case模擬之比較 ----------------------- 96

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