臺灣博碩士論文加值系統

本論文實現一個具三種模式且可重組14位元2GS/s或12位元4GS/s電流源式數位類比轉換器。針對各種數位類比轉換器的應用，設計出三種模式，分別為超取樣模式，奈奎氏模式及超越奈奎氏頻帶模式。為實現可符合各種應用且具有最佳效能的數位類比轉換器，設計之數位類比轉換器提出許多技術以提升輸出表現。針對電流源式數位類比轉換器設計中電流源不匹配問題，採用最小切換動態元件匹配和資料權重平均法這兩種不同的動態元件匹配演算法，可配合不同的應用切換，以降低不匹配造成在各種模式中的諧波失真。在超取樣模式中，則以資料權重平均法提升在窄頻中的輸出表現。至於超越奈奎氏頻帶，則提出不同於現有技術的切換方式，使其應用於超越奈奎氏頻帶有極佳的輸出表現。不僅可使第三奈奎氏頻帶訊號衰減量低於10dB，且無雜訊動態範圍更可維持65dB以上的規格。整體效能更是優於現有發表成果。
此電流源式數位類比轉換器之實現是採用TSMC 90奈米，1P9M互補金氧半導體製程，主動電路面積僅0.082平方毫米。量測結果顯示，此數位類比轉換器可達到在1.1GS/s下從低頻到0.55GHz的SFDR均大於60dB，且14-bit奈奎氏頻帶中的效能指數和世界頂尖的作品相比均為最佳。

In this thesis, a triple-mode 14-bit 2GS/s or 12-bit 4GS/s reconfigurable current-steering digital-to-analog converter (DAC) is presented. For different DAC applications, triple mode is proposed, which means over-sampling mode, Nyquist mode, and over-Nyquist mode. The target of this work is that using a single DAC chip to fulfill all of the applications and with better performances than any state-of-the-art work. For this target, many techniques are proposed to improve the performances. In current-steering DAC design, current source mismatch is a main problem. Minimum switching dynamic element matching (MSDEM) and data weighted averaging (DWA) are adopted to process the harmonic distortion caused by mismatch. In addition, for over-sampling mode, DWA is used to improve the performance in narrow band. Moreover, for over-Nyquist mode, a novel method is proposed which makes the signal consumption 〈 10dB and spurious-free dynamic range (SFDR) 〉 65 dB up to 3rd Nyquist band.
The current-steering DAC is fabricated in TSMC 90nm 1P9M CMOS technology with only 0.082mm2 of active area. The measurement results show that the DAC achieves 〉60dB SFDR from dc to 0.55GHz at 1.1GS/s and the 14-bit Nyquist band performance is the best in figure of merit (FOM) comparing to state-of-the-art works.

摘要 I
Abstract II
Acknowledgements III
Table of Contents IV
List of Tables VI
List of Figures VII
Chapter 1 : Introduction 1
1.1 Motivation 1
1.2 Organization 5
Chapter 2 : Fundamental of Digital to Analog Converters (DACs) 6
2.1 Ideal DAC 7
2.2 Static Performances 8
2.3 Dynamic Performances 12
2.4 Sample-and-Hold Response 17
Chapter 3 : Techniques for Linearity Enhancement 20
3.1 Suppression of Mismatch Effect 21
3.1.1 Current Source Mismatch Effect 22
3.1.2 Noise Shaping Analysis of MSDEM and DWA 26
3.2 Reduction of Output Transition Nonlinearity 36
3.3 Compensation of Finite Output Impedance 44
3.4 Performance Improvement in Over-Nyquist Band 46
Chapter 4 : Circuit Design and Implementation 52
4.1 Circuit Design Details 52
4.1.1 Build-in Testing Circuits 53
4.1.2 Reconfigurable Circuits 56
4.1.3 Switch Driver 60
4.1.4 Current Cell Array 63
4.1.5 Clock Receiver and Buffer 68
4.1.6 Hysteresis Circuit Design and Consideration 71
4.2 Whole Chip Layout and consideration 72
4.3 Summary of Simulation Results 76
4.3.1 Simulation Results of Nyquist Mode 76
4.3.2 Simulation Results of Over-sampling Mode 80
4.3.3 Simulation Results of Over-Nyquist Mode 81
Chapter 5 : Performance Measurements 84
5.1 Measurement Setup 84
5.2 PCB Design Consideration 86
5.3 Nyquist Mode Measurement Result 88
5.4 Over-Nyquist Mode Measurement Result 91
Chapter 6 : Conclusion and Future Work 94
Reference 97

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