跳到主要內容

臺灣博碩士論文加值系統

(216.73.216.167) 您好!臺灣時間:2025/10/31 19:56
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:古依純
研究生(外文):Ku, I-Chun
論文名稱:電荷缺陷儲存式快閃記憶體側向位移之模型分析
論文名稱(外文):Analysis and Modeling of Lateral Migration for Charge Trapping Flash Memory
指導教授:連振炘施君興
指導教授(外文):Lien, ChenhsinShih, Chun-Hsing
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:50
中文關鍵詞:快閃記憶體缺陷側向位移
外文關鍵詞:flash memorytraplateral migration
相關次數:
  • 被引用被引用:0
  • 點閱點閱:375
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
近年來,矽-二氧化矽-氮化矽-二氧化矽-矽(SONOS)型記憶體逐漸成為非揮發記憶體中的主流,隨著製程的演進,SONOS型記憶體亦面臨到尺寸微縮後可靠度之問題,在主要的微縮議題,即此儲存於氮化矽層中載子將會出現側向遷移(Lateral Migration)現象,由於操作上所產生的熱擾動及多次循環讀寫/抹除後,造成電荷缺陷儲存式快閃記憶體其儲存載子濃度與分布的改變,進而往通道內部方向不斷延伸,使得臨界電壓發生變異(Threshold Voltage Variations)進而影響記憶體單元的操作。
本文中,提出注入氮化矽缺陷層中的載子在經過時間與電壓的操作下會進行側向的擴散之模型,利用擴散方程式計算載子在擴散後對時間與位置之分布,在加入臨界電壓變異模型,將所儲存的載子對臨界電壓值的貢獻皆歸於平帶電壓中,如此便可以得到在理想情況中,電荷以擴散方式之側向遷移對長通道元件的臨界電壓變異模型。再利用二維元件模擬軟體(MEDICI)來做電性分析,將不同的通道長度中,以量化的方式,對氮化矽中的載子的設定,以達到將固定載子數量放在捕捉層之目的,改變預設之載子濃度與側向擴散之長度,以分析載子分布對元件電性之影響,根據模擬之電性結果與所建立之物理分析模型比較,希望發展及建立側向遷移行為之物理分析模型。









Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lowing operating voltage and two-bit storage. However, it also a great challenge for that the local distributions of trap charges will be lateral migrated after thermal various or endurance operation. Since the gate length of the cell devices are continued to scale down, it is crucial to realize the impacts of lateral migration on device characteristics for the programmed and the erased SONOS cells, specially the variations of threshold voltage.
In this paper, using diffusion equation to realize the retribution of trapped charge, and then developing the model from gate voltage equation to provide a sound understanding of threshold voltage variations due to lateral migration. Through two-dimensional TCAD simulator MEDICI, the trapped charges are distributed uniformly within the nitride layer. And the conservation of the total trapped charges is assumed in this study. The characteristic lateral migration lengths are used to indicate the degree of lateral migration. Compare the results between the simulation and the modeling to analysis what is the reason in the difference. Eventually, we hope to develop a theoretical model to explain the retention loss characteristics by lateral-migrated trapping charges.
中文摘要 Ⅰ
Abstract Ⅱ
致謝 Ⅲ
目錄 Ⅳ
圖例說明 Ⅵ
表例說明 Ⅷ
第一章 非揮發性記憶體之簡介
1.1研究背景 1
1.1.1浮動閘式快閃記憶體的概念與瓶頸 2
1.1.2電荷缺陷儲存式快閃記憶體概念與發展 3
1.2電荷缺陷儲存式記憶體微縮之議題 4
1.3研究動機 4
1.4論文架構 5
第二章 側向位移之原理探討
2.1載子傳輸機制 10
2.1.1躍遷(Hopping Transport)現象 10
2.1.2擴散(Diffusion)現象 11
2.2臨界電壓變異模型 12
2.3次臨界擺幅 14
2.4熱逸散 15
2.5可靠度之探討 16
第三章 等效擴散模型
3.1等效擴散現 21
3.2等效擴散模型 22
3.3高斯函數之近似 24
3.4臨界變異電壓模型 25
3.5側向位移模擬架構 27
第四章 模型分析與數值模擬結果討論
4.1ㄧ維模型分析之探討 30
4.2二維數值模擬分析之探討 31
4.2.1短通道效應之影響 31
4.2.2 m因子理論 32
4.2.3次臨界現象 33
4.2.4表面位能之探討 35
4.3模型分析與數值模擬之比較 36
第五章 結論與未來展望 46
參考文獻 47

[1] Pavan Paolo, Bez Roberto, Olivo Piero and Zononi Enrico,“Flash Memory Cell-An Overview” Proc. IEEE, pp. 1248-1271, 1997.
[2] R. Bez,. E. Camerlenghi, A.Modelli, A. Visconti, “Introduction to flash memory,” Proc. IEEE, vol. 91, pp. 489 -502, 2003.
[3] International Technology Roadmap for Semiconductor, 2007 edition.
[4] C. Y. Lu, T. C. Lu, R. Liu, “Non-Volatile Memory Technology-Today and Tomorrow,” Proc. of 13th International Symposium on Physical and Failure Analysis of Integrated Circuit, Singapore, p.18, 2006.
[5] J. H. Kim, and J. B. Choi, “Long-term electron leakage mechanism”.
[6] K. Prall, “Scaling Non-Volatile Memory Below 30nm,”in Proc. NVSMW, pp. 5-10, 2007.
[7] H. A. R Wegener, A. J. Lincoln, H. C. Pao, M. R. O'connell, R. E. Oleksiak, H. Lawrence, “The Variable-Threshold Transistor, A New Electrically-Alterable, Nondestructive Read-Only Storage Device,” in IEDM Tech. Dig., 1967.
[8] M. H. White, D. Adams and J. Bu. “On the Go With SONOS,” IEEE Circuits Devices Mag., pp. 22-31, 2000.
[9] C. H. Lee, et al., “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit flash memories,”in IEDM Tech. Dig., 2003, pp.613-616.
[10] M. Grossi, M. Lanzoni, and B. Ricco, ” Program schemes for multilevel flash memories,” in Proc. IEEE, vol. 91, pp. 594-601, 2003.
[11] K. -H. Kuesters, C. Ludwing, T. Mikolajick, N. Nagel, M. Specht, V. Pissors, N. Schulze, E. Stein, and J. Willer, “Future trends in charge trapping memory” in Proc. ICSICT, pp.740-743, 2006.
[12] M. Janai,, B. Eitan,, A. Shappir, E. Lusky, I. Bloom, and G. Cohen, “Data Retention Reliability Model of NROM Nonvolatile Memory Products,” IEEE Trans Dev. and Material Reliability, vol. 4,, pp.404-415, 2004.
[13] N. K. Zous, M. Y. Lee, W. J. Tsai, A. Kuo, L. T. Huang, T. C. Lu, C. J. Liu, T. Wang, W. P. Lu, W. Ting, J. Ku, and C. -Y Lu,” Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and Its Qualification Methodology,” IEEE Electron Device Lett., vol. 25, pp. 649-651, 2004.
[14] B. Y. Choi, 1, B. -G Park1, Y. K. Lee, et al.,” Highly Scalable and Reliable 2-bit/cell SONOS Memory Transistor beyond 50nm NVM Technology Using Outer Sidewall Spacer Scheme with Damascene Gate Process,” in Proc. VLSI, pp. 118-119. 2005.
[15] E. Lusky,, Y. S. Diamand, G. Mitenberg, Shappir, I. Bloom, and B. Eitan, “Investigation of channel hot electron injection by localize charge-trapping nonvolatile memory devices,” IEEE Trans Electron Devices, vol. 51, pp. 444-451, 2004.
[16] W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, T. Wang, S. Pan. and C.-Y. Lu, “Cause of data retention loss in a nitride based localize trapping storage flash memory cell,”IEEE IRPS, pp. 34-38, 2002.
[17] Yutaka Okuyama, Shiro Kamohara, Yukiko Manabe, and Kousuku Okuyama, “Monte Carlo Simulation of Stress-Induced Leakage Current by Hopping Conduction via Multi-Traps in Oxide,” in IEDM Tech. Dig. 1998. pp. 905-908.
[18] Shiro Kamohara, Donggun Park,, and Chenming Hu, “Deep-Trap SILC (Stress Induce Leakage Current) Model For Nominal and Weak Oxides,”Proc. IEEE, pp. 57-61, 1998.
[19] David Fuks, Arnold Kiv, Yakov Roizin, Micha Gutman, Rachel Avichil-Bibi, and Tatyana Maximova, “The Nature of HT Vt Shift in NROM Memory Transistors,” IEEE Trans. Electron Devices, vol. 53, pp. 304-313, 2006.
[20] James D. Plummer, Michael D. Deal, and Peter B. Griffin,“Silicon VLSI Technology,”Pearson International Edition, Prentice Hall, 2000.
[21] Ben G. Streetman, and Sanjay Banerjee, “Solid State Electronic Devices”5th Edition Prentice Hall, 2000.
[22] Richard S. Muller, Theodore I. Kamins, and Mansun Chan,“Device Electronic for Integrated Circuits,”3rd Edition, Wiliey, 2003.
[23] R. A. Walliams and M. M. E. Beguwala, “The effect of electrical conduction of Si3N4 in the discharge of MNOS memory transistors,”IEEE Trans. Electron Devices, vol. ED-25, pp. 1019-1030, 1978.
[24] O. K. Lui, and P. Migliorato, “A new generation-recombination model for device simulation including the Poole-Frenkel effect and phononassisted tunneling,”Solid State Electron, vol. 41 pp. 575-583, 1997.
[25] K. A. Nasyrow, V. A. Gritsenko, M. K. Kim, H. S. Chae, S. D. Chae, W. I. Ryu, J. H. Sok, J. –W. Lee, and B. M. Kim, “Charge transport mechanism in metal-nitride-oxide-silicon structure,”IEEE Electron Device Lett., vol. 23, pp. 336-338. 2002
[26] Synopsys MEDICI User’s Manual, Synopsys Inc., Mountain View, CA, 2006.
[27] Yuan Taur and Tak H. Ning,“Fundamentals of Modern VLSI Devices, ” Second Edition, Cambridge University Press, 1998.

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top