臺灣博碩士論文加值系統

近年來晶片趨向輕薄短小、低耗電、低成本與多功能的需求，故晶片在系統中可使用的空間愈來愈小，因此發展3-D 多晶片堆疊封裝（Stacked-Die Packaging; SDP）技術是目前前瞻的封裝構想。而當晶片數量增加時，必須經由減少晶片厚度來達到既有晶片堆疊的空間，此外SDP多晶片封裝若有一顆IC失效，將連帶造成整個IC無法運作，不僅影響整體良率外，更會導致成本的大幅提高。目前 SDP技術在封裝製程中的關鍵就是前端之超薄晶圓針測(Thin Wafer Probing)技術。故如能藉由實驗、分析模擬的方式，來研究在超薄晶圓針測時可應用的優化參數，本研究利用三點彎矩方法來探討薄化晶圓之破壞強度與破壞應力。本研究另一重點是建立晶圓針測溫控系統，將探針與銲墊放置在環境加熱爐中控制溫度，觀察不同針測行程之針測結果，並探討探針頭對銲墊之接觸力、銲墊之刮痕大小與刮痕深度。本研究之成果將可做為針測時薄晶圓能承受的應力指標，並了解鋁銲墊在不同環境溫度下受到探針之接觸的刮痕大小，有助於對薄晶圓針測的選擇與應用。

Light weight, small size, low voltage, and low cost are the mainly request of high performance IC product; on the other hand, it also means the spacing for IC system is very limited. Therefore newly development of 3D Stacked-Die Packaging (SDP) is the current important direction for advance packaging technique. SDP need to be supported with thin wafers so that the stacking dies could maintime the spacing limitation. However one failure die could cause whole packaging failure that could lead to lower the yield rate and increasing the manufacturing cost. Currently, one of the key technologies need to improve yield rate is the Thin Wafer Probing Technique. Researches focus on developing experimental methods and computer simulation skills to study the optimized probing parameters for ultra-thin wafer. In this thesis , we studied the fracture strength and failure stress of thin wafers with three-point bending method. We also set up temperature controlled system; Both probe and bonding pad could put in the temperature controlled system, observe the contact force and mark length and mark depth. The achievement from this research could reveal the limited stress index in thin wafer and also understand how temperature level could effect the scratch size and contact force under different probing overdrive conditions that help the engineer to select better parameter of probing process.

第一章 緒論 1
1-1 研究動機 1
1-2 研究目的 8
1-3 文獻回顧 9
1-3-1 三點彎矩實驗對晶圓強度的探討 9
1-3-2 探針針測銲墊刮痕之損傷分析 15
1-3-3 文獻回顧總結 24
1-4 研究方法、進行步驟與流程 25
第二章 超薄晶圓強度測試實驗 29
2-1 Three-Point-Bending實驗目的與設計 29
2-1-2 3-P-B試片之製作 33
2-2 3-P-B實驗設備與架構 35
2-3 3-P-B實驗方法與步驟 37
2-4 實驗結果與討論 39
第三章 薄晶圓強度測試有限元素模擬 45
3-1 有限元素模型之建立 45
3-1-2 邊界設定與材料性質給定 48
3-2 有限元素模型驗證 49
3-3 實驗結果與討論 52
第四章 溫控環境之晶圓針測實驗 55
4-1 實驗設備與架構 56
4-2 環境溫度之給定與量測條件 59
4-3 實驗方法與步驟 62
4-4 實驗結果與討論 66
4-4-1 錸鎢探針對鋁銲墊之針測力量 67
4-4-2 鋁銲墊之刮痕長度 72
4-4-3 鋁銲墊之刮痕深度 77
第五章 結論與未來研究方向 83
5-1 結論 83
5-2 未來研究發展 85
參考文獻 86

[1]Itoh, T., Kataoka, K., Suga, T., “Characterictics of Low Force Contact Process for MEMS Probe Cards, ”Sensors and Actuators A 97-98, pp. 462-467, 2002.
[2]Cerprobe Corporation Application Note, in http://www.cerprobe.com, March , 2000.
[3]Chae, S.H., Zhao, J.H., “Effect of Dicing Technique on the Fracture Strength of Si Dies With Emphasis on Multimodal Failure Distribution, ” IEEE Transactions on Device and Materials Rellability vol. 10, no. 1, march , 2010.
[4]ASTM, “Standard Test Methods for Flexural Properties of Unreinforced and Reinforced Plastics and Electrical Insulating Materials, ” D790-03
[5]Wei, S., Zhu, W.H., Che, F.X., Wang, C.K., “Ultra-thin Die Characterization for Stack-die Packaging, ” United Test & Assembly Center Ltd (UTAC) Packaging Analysis & Design Center, 2007.
[6]Lee, W.E., Lim, B.K., Low, T.H., “Mechanical Characterization in Failure Strength of Silicon Dice, ”Packaging Analysis & Design Center United Test & Assembly Center Ltd (UTAC), 2004
[7]Tsai, M.Y., Lin, C.S., “Testing and Evaluation of Silicon Die Strength, ”IEEE Transactions on Electroncs Packaging Manufacturing, Vol. 30, No. 2, 2007
[8]Tsai, M.Y. , Chen, C.H., “Evaluation of Test Methods for Silicon Die Strength, ” Department of Mechanical Engineering, Chang Gung University, 2008
[9] Stephan, S., Matthias, E., Christof, L., Karlheinz, B., Jorg, B., “Investigations of The Influence of Dicing Techniques on The Strength Properties of Thin Silicon, ” Fraunhofer-Institute for Mechanics of Materials, 2007
[10]Stephan, S., Matthias, E., Jorg, B., “Influence of the Thickness of Silicon Dies on Strength, ” IEEE 7th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE, 2006
[11] Chang, H.Y., Pan, W.F., Shih, M.K., Lai, Y.S., “Geometric design for ultra-long needle probe card for digital light processing wafer testing, ” Microelectronics Reliability 50 pp. 556–563, 2010
[12] Liu, D.S., Chang, C.M., “Novel Analysis Model for Investigation of Contact Force and Scrub Length for Design of Probe Card, ” Microelectronics Reliability 50 pp.872–88, 2010
[13] 陳國明, “微電子元件針測壓痕之深度預測及對錫鉛凸塊電子遷移影響之研究, ”清華大學動力機械工程研究所論文, 2003.
[14] Broz, J.J., Rincon, R.M., “Probe Contact Resistance Variations During Elevated Temperature Wafer Test, ”IEEE Itc Interational Test Conference, pp. 396-405, 1999.
[15] 施孟鎧, “晶圓針測參數分析之測試方法與應用有限元素模擬, ”中正大學機械工程研究所論文, 2002.
[16] 黃惟孝, “晶圓針測探針之接觸電阻量測方法與失效分析, ”中正大學機械工程研究所論文, 2003.
[17] Qing, T., Beddingfield, C., Mistry, A., “Reliability Evaluation
of Probe-before-bump Technology, ”IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp. 320-324, 1999.
[18] 劉士銘,“多層探針之排列設計方法-應用有限元素分析,”中正大學機械工程研究所論文, 2005.
[19] Hotchkiss, G., Ryan, G., Subido, W., Broz, J., Mitchell, S., Rincon, R., Rolda R., and Guimbaolibot, L.,“Effect of Probe Damage on Wire Bond Integrity,”IEEE Electronic Components and Technology Conference, 2001
[20] Chen, K.M., Chiang, K.N., “Impact of Probing Procedure on Flip Chip Reliability, ” Microelectronics Reliability, pp. 123-130, 2002
[21] Hibbeler, R. C., “Statics and Mechanics of Materials, ” 1993
[22] Weeden, O.,“Probe Card Tutorial,”(keithley), in http://www.keithley.com
[23] Introduction to Probe Card, in http://www.mpi.com.tw
[24] Non-destructive Cleaning to Maintain High Wafer Yield and Extend Probe Card Life, in http://www.inttest.com
[25] Enhanced Standard Cantilever Epoxy Probe Cards, in http://www.knstaiwan.com
[26] Leslie, B., Matta, F., “Membrane Probe Card Technology, ” Test Conference, 1988. Proceedings. International pp. 601-607, 1988.