臺灣博碩士論文加值系統

本論文探討最高位元優先處理架構之設計問題，並提出新的最高位元優先處理架構設計方法俾用於超大型積體電路實現，此架構尤其適用在多媒體與通訊系統。我們將以視訊壓縮中移動預測為例，驗證我們的設計。實現的結果顯示，我們所提出之最高位元優先處理架構設計在相同的晶片面積下，其「絕對差值和」之運算效能為傳統位元並行處理方式的五點零四倍。
在過去，採用線上運算電路的最高位元優先處理架構被廣泛的應用在提高計算效能。然而，採用冗餘編碼數系之線上運算電路，其實現成本較傳統的位元並行處理方式多出一倍以上。但也因冗餘編碼可以吸收算數運算中產生的進位或借位，使進位傳遞鏈波得在相鄰的兩個位元中被打斷。故自西元一九六零年以來，最高位元優先處理的研究主要集中在設計高效能算數元件。本論文提出新的最高位元優先處理架構使運算量降低並保有原來高效能之優點。以移動預測為例，新系統把移動向量之所有候選區塊其絕對差值和及比較運算，依最高位元優先運算的方式拆解至位元層次。這些被拆解後的比較運算會被插入至絕對差值和之後，以分辨移動向量，此動作一直持續到移動向量被找到。過程中，如候選區塊的絕對差值和大到確定不可能成為移動向量，則此候選區塊的剩餘運算就可完全移除。因人類的視覺及聽覺不是百分之百的靈敏。所以在多媒體系統中，存在大量不需要完全精確的演算法，如移動向量搜尋與量化的動作。故此方法非常適合於多媒體系統實現。此外在通訊上，資料通道特性會隨時變化且無法被精確的模擬，使本設計方法在通訊應用也將有很大的潛力。總之，新的架構設計方法能偵測並移除包藏在演算法中冗餘的運算，並維持線上運算電路之高效能特性。
在實現上，新的位元優先處理架構系統也面臨一連串設計上的問題，包括：如何有效將原始演算法拆解至位元運算、重組運算且無誤的移除冗餘運算、線上運算的電路最佳化及找出位元層次平行度以增加系統效率。以上困難均倍於傳統設計方法。論文中以移動預測為例，提出完整的解決方案。在系統層次上，我們分析了移動預測的演算法並發展其最高位元優先處理架構。而C語言程式用以模擬系統效率。詳細的演算法效能與視訊特性分析也會被論及。除此之外，為降低外部記憶體頻寬我們也設計了特殊的記憶體子系統。在電路層次上，關鍵電路「線上運算比較器」，負責移除冗餘運算。它的效能將決定整個系統效率。再者，絕對差值和之線上運算元件必須最佳化以降低電路複雜度。最後，高效能陣列處理器設計及整體MPEG視訊壓縮架構在本論文中也將被提出。此設計利用位元間的資料平行度，達成一區塊預測中任一畫素只被讀取一次的要求。我們會就實現的結果作比較，包括：邏輯閘用量及效能與傳統設計之比較。我們也提供詳盡的系統層次分析。結果顯示，我們的最高位元優先處理架構於相同的邏輯閘數目時，為傳統設計效能的五點零四倍。其中最高位元優先處理移動預測可以減少百分之四十七點四的運算，而線上運算的電路實作則提供另外二點一六倍的效益。

This dissertation explores the issues of the MSD-first processing and derives a novel MSD-first architecture strategy for VLSI implementations. The architecture is very suitable for the multimedia and communication systems. We demonstrate this design methodologies by an ME example. The implementation results show that our MSD-first strategy totally supports 5.04 times SAD (summation of absolute difference) operations per unit area of the conventional digit-parallel ones.
The MSD-first processing adopts the on-line arithmetic components that are widely used for speed-up computations in the past. However, the redundant number system of the on-line arithmetic makes its implementation cost, which doubles that of the digit-parallel approaches. Because the redundant number system absorbs the possible carry (or borrow) of the arithmetic operations, the carry propagation chain will be broken between adjacent digit operations. Beginning in the 1960’s, the major researches of the MSD-first processing still focus on the high-performance arithmetic component design. This dissertation proposes a novel MSD-first architecture design approach for reducing arithmetic operations. For the ME example, our system decomposes the SAD and comparison operations of all the candidates into digit level with MSD-plane first. These comparisons are interleaved into SAD’s to distinguish MV till the appearance of the best matching. The related operations of the candidates with large SAD enough not to be MV can be also removed during the processing. The system is suitable for the multimedia applications since the human perception of the visual and audio quality is not fully sensitive. There are numbers of algorithms with inaccurate computation requirements in a multimedia system such as quantization and the search of MV. Moreover, the time-variable characteristics of the communication channel are also suitable for the MSD-first implementations. To sum up, the novel architecture design methodology detects and removes those digit-level redundant computations of the algorithms embedded as well as preserving the high throughput of on-line arithmetic components.
For implementations, the novel MSD-first architecture faces a series of design issues, which contain decomposing the original algorithm into the digit-level operations, reorganizing them to remove the possible redundant operations, the on-line arithmetic component optimization and deriving the digit-level parallelism to boost the system performance. Their considerations are all different from the traditional digit-parallel input ones. The dissertation proposes the total solutions for the ME example. In the system level, we analysis the ME algorithm and derive the MSD-first ME with its architecture. An essential C-language program simulates the system efficiency. The detail result versus the video characteristics is also discussed. Besides, the memory subsystem design for the external memory provides a solution to reduce the memory I/O bandwidth. In the circuit level, the key component of the on-line arithmetic comparator manipulates the removes of the digit-level SAD operations. This performance dominates the system efficiency. Moreover, the on-line arithmetic SAD is optimized for low circuit complexity. A performance-driven design of the systolic array processor and the complete MSD-first architecture for the MPEG video compression are shown in the dissertation. This design explores the digit-level parallelism of the MSD-first ME, which achieves one time access for the MV searching of a MB. We will compare the results, which include the gate count and the performance, with a traditional digit-parallel inputs design. Finally, a detail analysis of our design methodology is given. The result shows our proposed MSD-first strategy yields 5.04 times hardware efficiency (MV/gate_count in ‘SUZIE’). The MSD-first ME removes 47.4% digit-SAD operations and the on-line arithmetic implementation contributes the other 2.67 times gains.

1 Introduction………………………………………………………………....1
1.1 Number Systems ……………………………………………………….2
1.2 Number Systems with Hardware Implementations …………………….4
1.3 Previous Works of Signed-Digit Number Processing ……………….10
1.3.1 MSD-First On-Line Arithmetic Components ……….………….10
1.3.2 Digit-Parallel Processing for SD Number System ……………..14
1.3.3 MSD-First Digit-Serial Word-Overlapped Processing for
Recursive Digital Filters ………………………...……………...17
1.4 Summary of Digit-Level Processing ……………………………….…21
1.5 Dissertation Contribution and Organization ………………………….23
2 Distributed Arithmetic Based and Novel MSD-First Architectures …...27
2.1 MSD-First Systems …………………………………………………...28
2.2 DA Based MSD-First Architecture for Recursive Filters …………….30
2.2.1 Signed-Digit Distributed Arithmetic Algorithm ……………..…30
2.2.2 Basic SD-DA AR Filters ………………………………….……34
2.2.3 Word Overlapped SD-DA AR Filters …………………..………37
2.3 DA Based MSD-First Architecture for DCT/IDCT………………..… 40
2.4 Novel MSD-First Architecture Implementation without Redundant
Digit-Operations ……………………………..………………………..45
3 MSD-First Motion Estimation …………………………………………...48
3.1 Motion Estimation ……..……………………………………………...49
3.2 Introduction of MSD-First ME ……………………………………….51
3.3 MSD-First ME ………………………………………………………..55
3.3.1 Digit-Level SAD with Word-Level Comparison ……………..55
3.3.2 Digit-Level SAD with Digit-Level Comparison ……………...57
A. Normal Mode …………………………………………….58
B. Prediction Mode ………………………………………….59
3.4 Summary for MSD-First ME …………………………………………60
4 Simulation Results and Analysis of MSD-first Motion Estimation …....61
4.1 Algorithm Simulation Results …………...……………………………62
4.1.1 Simulation Specification and Environment …………………..62
4.1.2 Simulation Results………...…………………………………..63
4.1.3 Additional Simulations ………………………………………..67
4.2 Algorithm Property Analysis ………………………………………….70
4.3 Summary ……………………………………………………………75
5 MSD-First ME Architecture and Memory Subsystem ……………...….76
5.1 MSD-first ME System ………………………………………………...77
5.2 Memory Reorder on MSD-First ME Subsystem ……………………..78
5.3 Array Processor Architecture of MSD-First ME ……………………..81
5.4 Data Reuse of MSD-First ME architecture …………………………...90
5.4.1 Data Reuse of Local On-chip Memory ………………………...91
5.4.2 Data Reuse between Array Processors …………………………92
5.5 MSD-First Architecture for MPEG Video Encoding …………………94
5.6 Summary of MSD-First ME Architecture ….………………………....96
6 On-Line Arithmetic Implementations …………………………………...98
6.1 On-Line Arithmetic SAD …………………….……………………….99
6.1.1 Difference ………………………………………………..……99
6.1.2 Absolute ……………………………………………………100
6.1.3 Summation………………………………………………….101
6.2 Key Component: On-Line Arithmetic Comparator ………………….103
6.2.1 Decision Making of MSD-First Comparison ………………104
6.2.2 On-Line Arithmetic Comparator Circuit Design …………….105
6.2.3 Design Verification with Example ……..……………………110
6.3 Implementation Results and Performance Evaluations …………..….113
7 Conclusion and Future Work ……………………………………..…….117
References …………………………………………………………….……….119
VITA ………………………………………………...……………………….127

[1] S. Waser and M. J. Flynn, Introduction to Arithmetic for Digital Systems Designers, Holt, Rinehart and Winston, NY, 1982
[2] K. Hwang, Computer Arithmetic, John Wiley & Sons Inc., NY, 1979
[3] A. Svoboda, Digitale Informationswanler, Vieweg and Sohn, Braunschweig, Germany, 1960
[4] N. S. Szabo and R. I. Tanaka, Residue Arithmetic and Its Applications to Computer Technology, McGraw-Hall, NY, 1967
[5] J. Sklansky and M. Lehman, “Ultimate-speed adders,” IRE Trans. EC-12, no. 2, pp. 142-148, Apr. 1963
[6] O. J. Bedrji, “Carry-select adders,” IRE Trans. EC-11, no. 3, pp. 340-360, June 1962
[7] A. Avizienis, “Signed digit number representation for fast parallel arithmetic”, IRE Trans. Electron Computers, vol. EC-10, pp. 389-400, 1961
[8] Y. Harata, Y. Nakamura, H. Nagase, M. Takigawa, and N. Takagi, “A high-speed multiplier using a redundant binary adder tree,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 28-34, Feb. 1987
[9] M. D. Ercegovac, A General Method for Evaluation of Functions and Computations in a Digital Computer, Ph.D. Dissertation, Department of Computer Science, University of Illinois, Urbana-Champaign, Aug. 1975
[10] M. D. Ercegovac, “A general hardware-oriented method for evaluation of functions and computations in a digital computer,” IEEE Trans. Computers, vol. C-26, no. 7, pp. 667-680, July 1977
[11] K. S. Trivedi and M. D. Ercegovac, “On-line algorithms for division and multiplication,” IEEE Trans. Computers, vol. C-26, no. 7, pp. 681-687, July 1977
[12] M. D. Ercegovac, “On-line arithmetic: an overview,” Proc. SPIE, Real Time Signal Processing VII, vol. 495, pp. 86-93, 1984
[13] K. K. Parhi, VLSI Digital Signal Processing: Design and Implementation, John Wiley & Sons, Inc., NY, 1999
[14] A. Guyot, Y. Herreros, and J. Muller, “JANUS, an on-line multiplier/divider for manipulating larger numbers,” Proc. of 9th Symposium on Computer Arithmetic, pp. 106-111, 1989
[15] D. S. Phatak and I. Koren, “Hybrid signed-digit number systems: a nuified framework for redundant number representations with bounded carry propagation chains,” IEEE Trans. Computers, vol. 43, no. 8, pp. 880-891, Aug. 1994
[16] Y. Harata, Y. Nakamura, H. Nagase, M. Takigawa, and N. Takagi, “A high-speed multiplier using a redundant binary adder tree,” IEEE J. Solid-State Circuits, vol. SC-22, No. 1, pp. 28-34, Feb. 1987
[17] G. Privat, “A novel class of serial-parallel redundant signed-digit multipliers,” Proc. IEEE Int’l Symp. Circuits and Systems, pp. 2116-2119, 1990
[18] N. Takagi, H. Yassura, and S. Yajima, “High-speed VLSI implementation algorithm with a redundant binary addition tree,” IEEE Trans. Computer, vol. C-34, no. 9, pp. 789-796, Sept. 1985
[19] G. A. Ruiz and M. A. Manzano, “Self-timed multiplier based on canonical signed-digit recording,” IEE Proc. -Circuits Devices Syst., vol. 148, no. 5, pp. 235-241, Oct. 2001
[20] M. D. Ercegovac and T. Lang, “Fast multiplication without carry-propagation addition,” IEEE Trans. Computer, vol. 39, no. 11, pp. 1385-1390, Nov. 1990
[21] G. Privat and M. Renaudin, “Motion estimation VLSI architecture for image coding,” Proc. IEEE Int’l Conf. Computer Design, pp. 78-81, 1989
[22] S. G. Chen, “A unified bit-parallel architecture using redundant binary representation,” Proc. Int’l Phoenix Conf. Computers and Communications, pp. 91-96, 1989
[23] H. R. Srinivas and K. K. Parhi, “High-speed VLSI arithmetic processor architectures using hybrid number representation,” Proc. IEEE Int’l Conf. Computer design, pp. 564-571, 1991
[24] R. J. Singh and J. V. McCanny, “Systolic two-port adaptor for high performance wave digital filtering,” Proc. Int’l Conf. Application Specific Array Processors, pp. 379-388, 1990
[25] W. Diffie, “The first ten years of public key cryptography,” Proc. IEEE, vol. 76, pp. 560-577, May 1988
[26] D. S. Phatak, T. Goff, and I. Koren, “Constant-time addition and simultaneous format conversion based on redundant binary representations,” IEEE Trans. Computer, vol. 50, no. 11, pp. 1267-1278, Nov. 2001
[27] K.K. Parhi, D.G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital Filters- -Part I: Pipelining using scattered look-ahead and decomposition,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1099-1117, July 1989
[28] C. W. Wu and P. R. Cappello, “Application-specific CAD of VLSI second-order sections,” IEEE Trans. Acoust., Speech, Signal Processing, vol. 36, pp. 813-825, May 1988
[29] C. L. Wang, C.-H. Wei, and S. H. Chen, “Efficient bit-level systolic implementation of FIR and IIR filters,” IEEE J. Select. Areas Commun., vol. 6, pp. 484-493, Apr. 1988
[30] S. E. McQuillan and J. V. McCanny, “A systemic methodology for the design of high performance recursive digital filters,” IEEE Trans. Computer, vol. 44, pp. 971-982, Aug. 1995
[31] J. V. McCanny, R. F. Woods, S. E. McQuillan, and R. J. Singh, “Very high performance DSP chips based on most significant bit first arithmetic,” Proc. DSPX Exposition and Symp., pp. 289-297, Oct. 1993
[32] S. E. McQuillan and J. V. McCanny, “Algorithms and architectures for high performance recursive filtering,” Proc. Int’l Conf. Application Specific Array Processors, pp. 230-244, Aug. 1992
[33] R. F. Woods, S. C. Knowles, J. V. McCanny, and J. G. McWhirter, “Systolic IIR filters with bit level pipelining,” Proc. Int’l Conf. Acoustics, Speech, and Signal Processing, vol. 4, pp 2072-2075, Apr. 1988
[34] S. C. Knowles, R. F. Woods, J. G. McWhirter, and J. V. McCanny, “Bit-level systolic arrays for IIR filtering,” Proc. Inte’l Conf. Systolic Arrays, May 1988
[35] O. C. McNally, J. V. McCanny, and R. F. Woods, “Optimised bit level architectures for IIR filtering,” Proc. Inte’l Computer Design, pp. 302-306, Sept. 1990
[36] M. Lapointe, P. Fortier, and H. T. Huynh, “A new faster and simpler systolic structure for IIR filters,” Proc. Inte’l Symp. Circuits and Systems, vol. 2, pp 1227-1230, May 1990
[37] M. Andrews, “A systolic SBNR adaptive signal processor,” IEEE Trans. Circuits and Systems, vol. CAS-33, no. 2, pp. 230-238, Feb. 1986
[38] B. Koppenhöfer, “A novel architecture for a decision-feedback equalizer using extended signed-digit feedback,” Proc. Int’l Conf. Application-Specific Array Processors, pp. 490-501, Oct. 1993
[39] R. R. Rao and I. Chakrabarti, “High-performance compensation technique for the radix-4 CORDIC algorithm,” IEE Proc. Computers and digital techniques, vol. 149, no. 5, pp. 219-227, Sept. 2002
[40] R. R. Osorio, E. Antelo, and J. D. Bruguera, “Digit on-line large radix CORDIC rotator,” Proc. Int’l Conf. Application Specific Array Processors, pp. 246-257, July 1995
[41] T. S. Chang, C. Chen, and C. W. Jen, “New distributed arithmetic algorithm and its application to IDCT,” IEE Proc. Circuits, Devices, and Systems, vol. 146, no. 4, pp. 159-163, Aug. 1999
[42] A. Vandemeulebroecke, E. Vanzieleghen, T. Denayer, and P. Jespers, “A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor,” IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 748-756, June 1990
[43] A. Peled and B. Lin, “A new approach to the realization of nonrecursive digital filters,” IEEE Trans. Audio and Electroacoustics, vol. AU-21, pp. 477-485, Dec. 1973
[44] S. A. White, “Applications of distributed arithmetic to digital signal processing: a tutorial review,” IEEE ASSP Magazine, pp. vol. 6, no. 3, pp. 4-19, July 1989
[45] K. P. Lim and A. B. Premkumar, “A modular approach to the computation of convolution sum using distributed arithmetic principle,” IEEE Trans. Circuits and Systems-II Analog and Digital Signal Processing, vol. 46, no. 1, pp. 92-96, Jan. 1999
[46] W. P. Burleson and L. L. Scharf, “VLSI design of inner-product computers using distributed arithmetic,” Proc. IEEE Int’l Symp. Circuits and Systems, vol. 1, pp 158-161, May 1989
[47] Y. T. Hwang and C. L. Su, “A new design approach and VLSI implementations of recursive digital filters,” Proc. IEEE Int’l Symp. Circuits and Systems, vol. 4, pp. 304-307, May 1996
[48] T. S. Chang, C. Chen, and C. W. Jen, “New distributed arithmetic algorithm and its application to IDCT,” IEE Proceedings- Circuits, Devices and Systems, vol. 146, no. 4, pp. 159-164, Aug. 1990
[49] S. Yu and E. E. Swartziander, “DCT implementation with distributed arithmetic,” IEEE Trans. Computers, vol. 50, vol. 9, pp. 985-991, Sept. 2001
[50] H. C. karathanasis, “A low ROM distributed arithmetic implementation of the forward/inverse DCT/IDCT using rotations,” IEEE Trans. Consumer Electronics, vol. 41, no. 2, pp. 263-272, May 1995
[51] L. G. Chen, J. Y. Jiu, and H. C. Chang, “Design and implementation of low-power DCT for portable multimedia terminals,” IEEE Workshop on Signal Processing Systems, pp. 85-93, Oct. 1998
[52] T. S. Chang, C. S. Kung, and C. W. Jen, “A simple processor core design for DCT/IDCT,” IEEE Trans. Circuits and Systems for Video Technology, vol. 10, no. 3, pp. 439-447, Apr. 2000
[53] K. R. Rao and P. Yip, ‘Discrete Cosine Transforms — Algorithms, advantages, applications,’ Academic, Boston, MA, 1990
[54] K. R. Rao and J. J. Hwang, Techniques and Standard for Image, Video and Audio Coding, Prentice Hall Inc., 1996
[55] T. Komarek and P. Pirsch, “Array architectures for block matching algorithms,” IEEE Trans. Circuits Systems for Video Technology, vol. 36, no. 10, pp. 1301-1308, Oct. 1989
[56] R. J. Jain and A. K. Jain, “Displacement measurement and its application in interframe image coding,” IEEE Trans. Commun., vol. 29, pp. 1799-1808 Dec. 1981
[57] T. Koga, K. Linuma, A. Hirano, Y. Iijima, and T. Ishiguro, “Motion compensated interframe coding for video conference,” Proc. NTC, pp. C9.6.1-5, Nov. 1981
[58] M. Ghanbari, “The cross-search algorithm for motion estimation,” IEEE Trans. Commun., vol. 38, pp. 950-953, July 1990
[59] V. Christopoulos and J. Cornelis, “A center-base adaptive search algorithm for block motion estimation,” IEEE Trans. Circuits Systems for Video Technology, vol. 10, pp. 423-426, Apr. 2000
[60] L. K. Su and R. M. Mersereau, “Motion estimation methods for overlapped block motion compensation,” IEEE Trans. Image Processing, vol. 9, pp. 1509-1521, Sept. 2000
[61] M. Bierling, “Displacement estimation by hierarchical block matching,” SPIE Conf., Visual Commun., Image Processing, vol. 1001, pp. 942-951, 1988
[62] B. Liu and A. Zaccaring, “New fast algorithms for the estimation of block motion vectors,” IEEE Trans. Circuits Systems for Video Technology, vol. 3, pp. 148-157, Apr. 1993
[63] Y. L. Chan and W. C. Siu, “New adaptive pixel decimation for block motion vector estimation,” IEEE Trans. Circuits Systems for Video Technology, vol. 6, pp. 113-118, Feb. 1996
[64] Y. Wang, Y. Wang, and H. Kuroda, “A globally adaptive pixel-decimation algorithm for block-motion estimation,” IEEE Trans. Circuits Systems for Video Technology, vol. 10, pp. 1006-1011, Sept. 2000
[65] J. Chalidabhongse and C. C. Kuo, “Fast motion vector estimation using multiresolution-spatio-temporal correlations,” IEEE Trans. Circuits Systems for Video Technology, vol. 7, pp. 477-488, June 1997
[66] F. Kossentini, Y. W. Lee, M. Smith, and R. K. Ward, “Predictive RD optimized motion estimation for very low bit-rate video coding,” IEEE J. Selected Areas in Communications, vol. 15, pp. 1752-1763, Dec. 1997
[67] A. Chimienti, L. Fanucci, R. Locatelli, and Saponara, “VLSI architecture for a low-power video codec system,” Microelectronics Journal, Elsevier Science, vol. 33, no. 3, pp. 417-427, 2002
[68] Z. L. He, C. T. Tsui, K. K. Chan, and M. L. Liou, “Low-power VLSI design for motion estimation using adaptive pixel truncation,” IEEE Trans. Circuits Systems for Video Technology, vol. 10, pp. 669-678, Aug. 2000
[69] Y. K. Lai and L. G. Chen, “A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm,” IEEE Trans. Circuits Systems for Video Technology, vol. 8, pp. 124-127, Apr. 1998
[70] L. K. Komarek and P. Pirsch, “Array architectures for block matching algorithms,” IEEE Trans. Circuits Systems, vol. 36, pp. 124-127, Apr. 1998
[71] J. C. Tuan, T. S. Chang, and C. W. Jen, “On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture,” IEEE Trans. Circuits Systems for Video Technology, vol. 12, pp. 61-72, Jan. 2002
[72] C. L. Su and C. W. Jen, “Motion estimation using on-line arithmetic,” Proc. IEEE Int’l Symp. Circuits and Systems, no. 1, pp. 683-686, 2000
[73] S. Y. Kung, VLSI Array Processor, Prentice-Hall Int’l Inc., NJ, 1988
[74] ‘Passport 0.35 micron, 3.3 volt, Optimum Silicon SC Library, CB 35OS142’, Avant! Corporation, Mar. 1998.
[75] “Synopsys: Design Compiler Tutorial,” Version 3.0b, Synopsysy Inc., June 1993
[76] Yeong-Kang Lai, Yeong-Lin Lai, Yuan-Chen Liu, Po-Chen Wu, and Liang-Gee Chen, “VLSI implementation of the motion estimator with two-dimensional data-reuse,” IEEE Trans. Consumer Electronics, vol. 44, no. 3, Aug. 1998
[77] K. M. Yang, M. T. Sun, and L. Wu, “A family of VLSI designs for the motion compensation block-matching algorithm,” IEEE Trans. Circuits Systems for Video Technology, vol. 36, pp. 1317-1325, Oct. 1989
[78] Seung Hyun and Moon Key Lee, “Flexible VLSI architecture of motion estimator for video image application,” IEEE Trans. Circuits Systems-II, vol. 43, pp. 467-470, Jun. 1996
[79] Luc De Vos and Michael Stegherr, “Parameterized VLSI architectures for the full-search block-matching algorithm,” IEEE Trans. Circuits Systems for Video Technology, vol. 36, pp. 1309-1316, Oct. 1989
[80] C. H. Hsieh and P. T. Lin, “VLSI architecture for block-matching motion estimation algorithm,” IEEE Trans. Circuits Systems for Video Technology, vol. 2, pp. 169-175, Jun. 1992
[81] T. Komarek and P. Pirch, “Array architectures for block matching algorithms,” IEEE Trans. Circuits Systems for Video Technology, vol. 36, pp. 1301-1308, Oct. 1989
[82] Hangu Yeo and Yu-Hen Hu, “A novel modular systolic array architecture for full-search block-matching motion estimation,” IEEE Trans. Circuits Systems for Video Technology, vol. 5, pp. 407-416, Oct. 1995