臺灣博碩士論文加值系統

在由上往下設計流程中,暫存器轉換階層設計是一種廣泛使用的數位電路設計描述方法,並且在此階層設計中, 最重要的事就是要確保設計功能的正確性. 然而,在最近的設計中,特殊功能晶片的設計是越來越複雜了, 並且如何對這些晶片執行驗證功能的工作也是越來越困難.因此在設計初期的情況中, 我們經常必須對擁有許多錯誤的晶片執行偵錯與除錯的工作.
在這篇論文中, 我們將提出一個新的架構來模擬暫存器轉換階層設計.
這個新的架構是建立在控制資料流程圖之上,並且藉由這個架構我們還可以產生暫存器轉換階層設計的自動偵錯程式與計算程式碼執行涵蓋範圍率.
我們所提出的模擬機構是模擬設計電路的週期行為. 它與兩種代表電路的方法 :一種是解析樹而另一種是控制資料流程圖, 來共同完成模擬的功能.其中解析樹能代表電路的組織架構,而控制資料流程圖能代表電路中控制訊號如何與資料流來互相影響發生作用.也因為有此兩種代表電路的方法, 我們能夠使用路徑列舉的技巧. 藉由使用這個技巧,我們可以計算每個時間週期中所執行的計算路徑,並且進而算出所有暫存器與輸出信號的數值.
我們也利用這種方法來做出應用.我們使用了計算最大公因數的電路來當作試驗程式的測試電路.並且成功地輸出正確的輸出反應與執行的路徑. 除此之外,模擬機構也可以輸出所有的計算路徑來幫助設計偵錯的步驟,或是產生測試平台的程序.

In the top-down design flow, the RTL(Register Transfer Level) design is one of the most widely used design representations for Digital IC's. Therefore, it is important to ensure that the design functionality is correct at this level. Recently, the ASIC design is more and more complex and the functional verification takes more and more efforts accordingly. Very often, we need to debug an RTL code that has been proven incorrect. In this thesis, we present an RTL simulation platform based on Control Data Flow Graph (CDFG). Upon this platform, RTL diagnosis or code coverage analysis can be performed more efficiently in the future. The proposed simulation mechanism is a cycle-based behavior simulation.
It incorporates both a parse tree and a CDFG to represent the RTL design. The parse tree represents the code structure, while the CDFG represents how the control signals interact with the data flow. Based on such a dual presentation, we will be able to perform simulation using the path enumeration technique. In this technique, we compute the value of each register and output signals by evaluating the computational path under execution for each clock cycle. As an experiment, we tested this program using a Greatest Common Divisor design. In addition to producing correct output responses and execution traces, the program can also report all computational paths to aid the subsequent design debugging process and/or testbench generation process.

摘要
致謝
第一章 簡介
第二章 解析器
第三章 內部取代電路
第四章 利用控制資料流程圖模擬的方法
第五章 實驗結果
第六章 結論
英文附錄

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