臺灣博碩士論文加值系統

我們提出一種新穎的分離式閘極結構於含有隱藏式選擇性閘極之半導體─氧化層─氮化矽─氧化層─半導體記憶體元件於NAND電路陣列結構上，此記憶體元件不僅製程簡單也能符合一般數位邏輯CMOS產品中的嵌入式非揮發性記憶體應用。論文中，我們探討在單一位元胞二位元操作中第二位元擾動效應產生的機制與抑制方式，並得到在操作多位元層級模式於此新穎的分離式閘極結構下，將不需要再考量二位元效應對記憶體元件產生的不理想效應，大大增加了位元判別區間與記憶體元件的可靠度。其中，我們操作此記憶體元件在單一位元胞二位元之多層級操作情況，在寫入與抹除操作的選擇上，我們則分別利用源極端注入(Source-Side-Injection)與能帶到能帶穿隧產生熱電洞(BTBTHH)的機制來完成，其操作在多位元的最低寫入速度仍將少於30us，寫入電流大小則大約是80nA，此時的隱藏式選擇性閘極與字元線控制閘極偏壓分別是0.45V與11V，而最快的抹除速度則可以在8ms被完成。
此特殊的新穎結構中主要的特點是包含了隱藏式選擇性閘極與分離式控制閘極。利用隱藏式選擇性閘極來形成多位元層級操作能得到較快速且精準的寫入過程與低功率消耗的特性；而分離式控制閘極則可以有效的抑制單一位元胞中二位元干擾效應的發生，降低臨界電壓所產生的波動範圍，進而維持一定的位元感測區間。此外，利用最佳化的ONO厚度可以達到非常優秀的抗閘極擾動、抗讀取擾動與長時間資料保存的能力；即使經過一萬次的重覆寫入/抹除的操作後，仍能夠保有原始的臨界電壓窗差值並在位元感測區間的範圍之內，而不會有位元判斷錯誤的結果發生。因此，此記憶體元件非常適合操作在單一位元胞二位元之多層級操作情況，它能擁有快速寫入、高可靠度與低功率消耗的特性表現。

For the first time, we propose the novel Wrapped-Select Gate SONOS (WSG-SONOS) memory with split-control gate in NAND architecture. The memory process is not only simple but also compatible with embedded non-volatile memory in conventional standard logic CMOS products. In this thesis, we demonstrate the physical mechanism and elimination of 2nd bit effect in 2 bit/cell operation. The results show that non-ideal 2nd bit effect would not be a consideration for the novel WSG-SONOS memory device with multi-level operation. It effectively increases the reliability of memory cell for the larger sensing margin of each state. Moreover, we operate the WSG-SONOS memory in 2 bit/cell mode with multi-level operation. The programming and erasing operations are performed by the Source-Side Injection (SSI) and Band-to-Band Tunneling Hot-Hole (BTBTHH), respectively. While operating the memory device in multi-level mode, the slowest program speed would be still less than 30us; the programming current is about 80nA as the wrapped-select gate voltage and word-line gate voltage are 0.45V and 11V, respectively. The fastest erase speed of 8ms is achieved.
The main features of this novel device contain the wrapped-select gate and split-control gate. By utilizing the wrapped-select gate to be an assistance gate, the SSI could accomplish the precisely multi-level operation in this memory cell. The SSI programming operation would achieve the low power consumption and high program speed’s characteristics in the memory device. In addition, the split-control gate could effectively decrease the variation of threshold voltage by eliminating the 2nd bit effect disturbance. It would remain the sense margin in this novel memory with multi-level operation. Moreover, the optimum thickness of ONO stack performs excellently for almost no gate disturbance, no read disturbance and long data retention. Even after 10K P/E cycling stress, the error bit wouldn’t happen in such device’s sensing window. As a result, the WSG-SONOS memory with split-control gate in NAND array is very adapted for the 2 bit/cell mode with multi-level operation. It owns the high program speed, low power consumption and high reliability characteristics for the flash memory technology demands. Thus, it has the larger application potential for flash memory market in the future.

Abstract (Chinese)………………………………………Ⅰ
Abstract (English)………………………………………Ⅲ
Acknowledgements (Chinese)……………………………Ⅴ
Contents……………………………………………………Ⅵ
Table Caption………………………………………………Ⅷ
Figure Caption……………………………………………Ⅷ

Chapter 1 Introduction
1.1 An Overview of Flash memory Technologies and Challenges………………………………………………………1
1.2 Introduction of NOR and NAND Architecture…………2
1.3 Introduction of Memory Device common operation Mode………………………………………………………………4
1.3.1 Program Technique…………………………………4
1.3.2 Erase Technique……………………………………6
1.3.3 Read Technique……………………………………7
1.4 Introduction of SONOS Flash Memory device……………………………………………………………9
1.5 Motivation…………………………………………………10
1.6 Organization of the thesis……………………………11

Chapter 2 Device Fabrication and Experimental Setup
2.1 Introduction………………………………………………20
2.2 Device Fabrication Flow…………………………………20
2.3 Measurement and Equipment Setup…………………… 21
2.4 Operation of Program/Erase/Read Mode………………23
2.5 Disturbance Phenomenon…………………………………24

Chapter 3 Studying of 2nd Bit effect and Simulated SSI mechanism of the WSG-SONOS memory with Split-Control-gate.
3.1 Introduction………………………………………………32
3.2 Results and Discussions…………………………………33
3.2.1 2nd Bit Effect Physical model…………………33
3.2.2 SSI mechanism Simulations………………………39
3.3 Summary………………………………………………………41

Chapter 4 Multi-level Operation Characteristics and Reliabilities of the WSG-SONOS memory with Split-Control-gate in NAND Array.
4.1 Introduction………………………………………………61
4.2 Results and Discussions…………………………………62
4.3 Summary………………………………………………………68

Chapter 5 Conclusions
5.1 Conclusions…………………………………………………82
5.2 Challenges and Recommendable Solutions……………82
5.3 Future Work…………………………………………………83

Reference…………………………………………………………85
Vita (Chinese)…………………………………………………91

References
Chapter 1
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Chapter 2
[2.1] Paul Robinson, “Flash Memory─Past Present And Future”, 4th Annual Multimedia Systems, Electronics and Computer Science, University of Southampton.
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[2.4] W.J. Tsai, S.H.Gu, N.K. Zeus, C.C. Yeh, C.C. Liu, C.H. Chen, Tahui Wang, Sam Pan, and Chih-Yuan Lu, “Cause of Data Retention Loss in a Nitride-Based Localized Trapping Storage Flash Memory Cell”, Reliability Physics Symposium Proceedings, 2002. 40th Annual, pp.34-38.
[2.5] W.J. Tsai, S.H.Gu, N.K. Zeus, C.C. Yeh, C.C. Liu, C.H. Chen, Tahui Wang, Sam Pan, and Chih-Yuan Lu, “Data retention behavior of a SONOS type two-bit storage flash memory cell”, IEDM Symp. Tech. Dig., 2001, pp. 719-722.
[2.6] Il Hwan Cho, Il Han Park, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park and Jong Duk Lee, “A novel NAND-type PHINES nitride trapping storage flash memory cell with physically 2-bits-per-cell storage, and a high programming throughput for mass storage applications.”, VLSI Symp. Tech. Dig., 2005, pp.116-117.
[2.7] Chien-Sheng Hsieh, Pai-Chu Kao, Chia-Sung Chiu, Chih-Hsueh Hon, Chen-Chia Fan, Wei-Chain Kung, Zih-Wun Wang, and Erik S. Jeng. “NVM Characteristics of Single-MOSFET Cells Using Nitride Spacers With Gate-to-Drain NOI”, IEDM Symp. Tech. Dig., 2001, pp. 719-722. IEEE Trans. Electron Devices, vol. 51 no. 11, 2004, pp 1811-1817.

Chapter 3
[3.1] Yong Kyu Lee, Suk Kang Sung, Jae Sung Sim, Ki Whan Song, Jong Duk Lee, Byung-Gook Park, Sung Taeg Kang, Chilhee Chung, Donggun Park and Kinam Kim “Scalable 2-bit silicon–oxide–nitride–oxide–silicon (SONOS) memory with physically separated local nitrides under a merged gate”, Solid-State Electronics, vol. 48. 2004. pp, 1771-1775.
[3.2] B.Y. Choi, B.-G. Park, J.D. Lee, H. Shin, Y.K. Lee, K.H. Bai, D.-D. Kim, D.-W. Kim, C.-H. Lee and D. Park, “Reliable 2-bit-cell NVM technology using twin SONOS memory transistor”, Electronics Letters, vol. 41. 2005. pp, 1086-1087.
[3.3] Hideto Tomiye, Toshio Terano, Kazumasa Nomoto and Toshio Kobayashi, “A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection”, VLSI Symp. Tech. Dig., 2002, pp.206-207.
[3.4] Byung Yong Choi, Byung-Gook Park, Yong Kyu Lee, Suk Kang Sung, Tae Yong Kim, Eun Suk Cho, Hye Jin Cho, Chang Woo Oh, Sung Hwan Kim, Dong Won Kim, Choong-Ho Lee, and Donggun Park, “Highly Scalable and Reliable 2-bit/cell SONOS Memory Transistor beyond 50nm NVM Technology Using Outer Sidewall Spacer Scheme with Damascene Gate Process”, VLSI Symp. Tech. Dig., 2005, pp.118-119.
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[3.6] Hang-Ting Lue, Tzu-Hsuan Hsu, Min-Ta Wu, Kuang-Yeu Hsieh, Rich Liu and Chih-Yuan Lu, “Studies of the Reverse Read Method and Second-Bit Effect of 2-Bit/Cell Nitride-Trapping Device by Quasi-Two-Dimensional Model”, IEEE Trans. Electron Devices, vol. 53 no. 1, 2006, pp 119-125.

Chapter 4
[4.1] Tom Coughlin, “Putting Portable Storage in Perspective”, Coughlin Associates, 2005.
[4.2] Jong-Ho Park, Sung-Hoi Hur, Joon-Hee Lee, Jin-Taek Park, Jong-Sun Sel, Jong-Won Kim, Sang-Bin Song, Jung-Young Lee, Ji-Hwon Lee, Suk-Joon Son, Yong-Seok Kim, Min-Cheol Park, Soo-Jin Chai, Jung-Dal Choi, U-In Chung, Joo-Tae Moon, Kyeong-Tae Kim, Kinam Kim and Byung-Il Ryu, “8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology”, IEDM Symp. Tech. Dig., 2004, pp. 873-876.
[4.3] Young-Joon Choi, Kang-Deog Suh, Yong-Nam Koh, Jong-Wook Park, Ki-Jong Lee, Yun-Jim Cho and Byung-Hoon Suh, “A high speed programming scheme for multi-level NAND flash memory”, VLSI Symp. Tech. Dig., 1996, pp.170-171.
[4.4] Youngwoo Park, Jungdal Choi, Changseok Kang, Changhyun Lee, Yuchoel Shin, Bonghyn Choi, Juhung Kim, Sanghun Jeon, Jongsun Sel, Jintaek Park, Kihwan Choi, Taehwa Yoo, Jaesung Sim, and Kinam Kim “Highly Manufacturable 32Gb Multi–Level NAND Flash Memory with 0.0098 μm2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology”, IEDM Symp. Tech. Dig., 2006, pp. 1-4.
[4.5] Kiran Pangal, Chintu Abraham, Michael Wang, Hien Nguyen, Jeffrey Coulter, Tom Begley and Steve Soss, “90 nm multi-level-cell flash memory technology”, IEEE Semiconductor Manufacturing, 2005, pp. 197-199.
[4.6] ZongLiang Huo, JunKyu Yang, SeungHyun Lim, SeungJae Baik, Juyul Lee, JeongHee Han, In-Seok Yeo, U-In Chung, Joo Tae Moon and Byung-II Ryu, “Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory”, VLSI Symp. Tech. Dig., 2007, pp.138-139.
[4.7] K Pangai, C Abraham, M Wang, N Hien, J Coulter, “90 nm multi-level-cell flash memory technology”, IEEE Semiconductor Manufacturing, 2005, pp. 197-199.

Chapter 5
[5.1] “Process Integration, Devices, and Structures.”, International Technology Roadmap for Semiconductors 2006 update
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[5.3] Sangmoo Choi. et al. “Improved metal–oxide–nitride–oxide–silicon-type flash device with high-k dielectrics for blocking layer”, Journal of Applied Physics, Vol. 94. 2003. pp. 5408-5410.
[5.4] Y. Q. Wang, D. Y. Gao, W. S. Hwang, C. Shen, G. Zhang, G. Samudra, Y.-C. Yeo, and W. J. Yoo, “Fast erasing and highly reliable MONOS type memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunneling stack”, IEDM Symp. Tech. Dig., 2006, pp. 1-4.
[5.5] Albert Chin, C. C. Laio, C. Chen, K. C. Chiang, D. S. Yu, W. J. Yoo, G. S. Samudra, T. Wang, I . J . Hsieh, S. P. McAlister, and C. C. Chi, “Low Voltage High Speed SiO2/AlGaN/AlLaO3/TaN Memory with Good Retention”, IEDM Symp. Tech. Dig., 2005, pp. 158-161.
[5.6] Hang-Ting Lue, Szu-Yu Wang, Erh-Kun Lai, Kuang-Yeu Hsieh, Rich Liu, and Chih Yuan Lu, “A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory”, VLSI Symp. Tech. Dig., 2007, pp. 1-2.
[5.7] Tzu-Hsuan Hsu, Hang Ting Lue, Ya-Chin King, Jung-Yu Hsieh, Erh-Kun Lai, Kuang-Yeu Hsieh, Rich Liu and Chih-Yuan Lu, “A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory”, IEEE Electron Device Lett., vol. 28, 2007, pp 443-445.
[5.8] Tzu-Hsuan Hsu, Hang-Ting Lue, Erh-Kun Lai Jung-Yu Hsieh Szu-Yu Wang, Ling-Wu Yanu Ya-Chin King, Tahone Yang , Kuang-Chao Chen, Kuang-Yeu Hsieh, Rich Liu, and CEhih-Yuan Lu, “A High-Speed BE-SONOS NAND Flash Utilizing the Field-Enhancement Effect of FinFET”, IEDM Symp. Tech. Dig., 2007, pp. 913-916.