臺灣博碩士論文加值系統

本論文中提出一個作為直接降頻接收器使用的全整合化頻率合成器，工作頻率在2.45G赫茲。文中從壓控振盪器的設計開始，以低功率消耗為設計主要考量，完成一消耗功率在1毫瓦以內的壓控振盪器（若操作在1.5伏特偏壓下，僅消耗53微安培）。除頻器部分則考量電流使用量，而採用較省電的整數N組態。
頻率合成器的量測結果如下：振盪頻率可調範圍在2351~2517百萬赫茲之間，鎖定所需時間約25微秒，距主頻1百萬赫茲遠處之相位雜訊為-88.4分貝/赫茲，寄生雜頻較主頻低14分貝；使用2.5伏特電壓源時消耗功率為58.625毫瓦。

Through this thesis, we demonstrated a fully integrated frequency synthesizer for direct conversion receiver. The working frequency is at 2.45GHz. We begin from the design of voltage controlled oscillator (VCO), devising it at the purpose of low power consumption, and established a VCO consumes less than 1mW (It consumes only 53μA when biased at 1.5V VDD).In the design of frequency divider part, we adopt integer-N topology which provides a less power consumption for low current use consideration.
The measurement results are listed as following: the oscillation frequency is tunable between 2351~2517MHz, locking time is approximately 25μs, phase noise is -88.4dBc/Hz@1MHz offset, spurious tones are less than carrier 14dB; the power consumption is 58.625mW using a 2.5V power supply.

CHINESE ABSTRACT………………………………………….……..I
ENGLISH ABSTRACT………………………………….……………II
ACKNOWLEDGMENT…………………………………..…………III
CONTENTS…………………………………………………………..IV
TABLE CAPTIONS……………………………………….………….VI
FIGURE CAPTIONS………………………………………………..VII
Chapter 1 INTRODUCTION……………………….………..…….1
1.1 Background and motivation……………………….…………………….1
1.2 Thesis organization……………………………………..………………...3
Chapter 2 VOLTAGE CONTROLLED OSCILLATOR (VCO) ....4
2.1 General design considerations……………………..……………………4
2.2 Design of 5.2-GHz Quadrature output VCO…………………………10
2.2.1 Design issues and introduction……………...………………10
2.2.2 Simulation results………………………….…………….……11
2.2.3 Measurement considerations and results………..…………15
2.2.4 Conclusions……………………..…..…….………………...…22
2.3 Design of an ultra low power 2.4-GHz VCO…………………………24
2.3.1 Design issues and introduction……………………………24
2.3.2 Simulation and measurement results………………………24
2.3.3 Conclusions…….…………..…..…………………………...…29
Chapter 3 FREQUENCY SYNTHESIZER………………………30
3.1 Architectures……………………………………………………………..31
3.2 VCO Design………………………………………………………………32
3.3 Fully programmable Frequency Divider……………………………33
3.3.1 Measurement results……………………………….…………35
3.4 Phase/frequency detector………………………………….……………38
3.5 Charge pump……………………………………………….……………39
3.6 Loop filter and loop bandwidth considerations……………………40
3.6.1 Design of loop filter………………...…………………………41
3.7 Whole circuit simulation…………………………..……………………43
Chapter 4 MEASUREMENT RESULTS………………………….46
4.1 Measurement considerations…………………………………………46
4.2 VCO measurement results……………………………………………48
4.3 Whole circuit Measurement…………………………..………………52
4.4 Summary of Measurement…………………………..………………….58
4.5 Measurement Discussions……………………………..………………59
Chapter 5 CONCLUSIONS AND FUTURE PROSPECTS…….68
5.1 Conclusions……………………………………………………………68
5.2 Future prospects………………………………………………………68
REFERENCES…………………………………………………………70

[1] Gwong-Wai Cheng, “A 5.25-GHz Fully Integrated CMOS Quadrature Voltage-Controlled Oscillator”, Thesis of Master’s Degree, Institute of communication, NCTU, Taiwan, ROC, JUN 2002.
[2] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators”, IEEE J. Solid-State Circuits, vol. 34, pp. 717-724, May 1999.
[3] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuit, vol. 35, June 2000.
[4] Porret, A.-S.; Melly, T.; Enz, C.C.; Vittoz, E.A. “Design of high-Q varactors for low-power wireless applications using a stand CMOS process,” IEEE Journal of Solid-State Circuits, Vol.35, pp.337-345, March 2000.
[5] Soorapanth, T.; Yue, C.P.; Shaeffer, D.K.; Lee, T.I.; Wong, S.S. “Analysis and optimization of accumulation-mode varactor for RF ICs” Symposium on VLSI Circuit Digest of Technical Papers. pp.32-33, 1998.
[6] J. Craninckx, M. Steyaert, “Wireless CMOS Frequency Synthesizer Design”, Kluwer Academic Publishers, 1998.
[7] Domine Leenaerts, Carel Dijkmans, Micheal Thompson, “A 0.18 μm CMOS 2.45 GHz Low-Power Quadrature VCO with 15% Tuning Range”, IEEE Radio Frequency Integrated Circuits Symposium, 2002, pp. 67-70.
[8] M. Tiebout, “A differential tuned 1.73GHz~1.99GHz Quadrature CMOS VCO for DECT, DCS1800, and GSM 900 with a phase noise over tuning range between -128dBc/Hz and -132dBc/Hz at 600kHz offset”, Proceedings ESSCIRC, pp. 444-447, 2000
[9] J. J. Kim, et. Al., “A Low-phase-noise CMOS LC oscillator with a ring structure”, ISSCC Digest of Technical Papers, pp. 200-201, Feb, 2000.
[10] J. T. Hwang, et. al., “New High Performance and Wide Range Tunable Two Stage 3GHz CMOS RF Hetero-linked oscillators”, Proceedings ESSCIRC, pp. 354-357, 1999.
[11] Sander L.J. Gierkink, Salvatore Levantino, Robert C. Frye, Vito Boccuzzi, “A Low-Phase-Noise 5GHz Quadrature CMOS VCO using Common-Mode Inductive Coupling”, ESSCIRC, 2002.
[12] Chih-Ming Hung, Brian A Floyd, Namkyu Park, Kenneth K. O, “Fully Integrated 5.35-GHz CMOS VCOs and Prescalers”, IEEE transactions on microwave theory and techniques, vol.49, NO.1, JAN 2001, pp. 17-22.
[13] Christopher Lam, Behzad Razavi, “A 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-μm CMOS Technology”, IEEE Journal of solid-state circuits, vol.35, NO.5, MAY 2000, pp.788-794.
[14] Sherif H. Galal, Hani F. Ragaie, Mohamed S. Tawfic, “On the Design and Sensitivity of RC Sequece Asymmetric Polyphase Network in RF Integrated Transceivers”, IEEE, 1999.
[15] Behzad Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
[16] Detlev Theil, Christian Durdodt, Andre Hanke, Stefan Heinen, Stefan van Waasen, Dietolf Seippel, Duyen Pham-stabner, Klaus Schmacher, “A Fully Integrated CMOS Frequency Synthesizer for Bluetooth “, IEEE Journal ,JULY 2001.
[17] F. M. Gardner, “Phaselock Techniques”, New York, NY: John Wiley & Sons, 1979.
[18] Ken Holladay, “Design a PLL for a Specific Loop Bandwidth”, Fujitsu Microelectronics, Inc., Oct 12, 2000.
[19] Dan H. Wolaver, “Phase-locked Loop Circuit Design”, Prentice Hall, New Jersey, 1991.
[20] Da Dalt, N.; Derksen, S.; Greco, P.; Sandner, C.; Schmid, H.; Strohmayer, K “A fully Integrated 2.4GHz LC-VCO Frequency Synthesizer with 3-ps Jitter in 0.18um Standard Digital CMOS Copper Technology”. Jul. 2002
[21] Chi-wa Lo, Howard Cam Luong, “A 1.5V 900MHz Monolithic CMOS Fast-Switching Frequency Synthesizer for Wireless Applications”, IEEE journal, JUN 2000.
[22] Hamid R. Rategh, Thomas H. Lee, “Multi-GHz Frequency Synthesis & division”, Kluwer Academic Publishers, 2002.
[23] Steve Williamson, “How to Design RF Circuits - Synthesizers”, IEE journal, 2000.