臺灣博碩士論文加值系統

　　本篇論文主旨在以超大型積體電路技術來設計與實現適應性多模態類神經模糊晶片(adaptive multimode neuro-fuzzy chip；AMNFC)晶片。晶片的設計引用高階合成 (high-level synthesis)的設計理念，將類神經模糊系統演算法的資料流程建構為data flow graph (DFG)的型式，再分別設計其內部適宜的排程(scheduling)與配置(allocation)策略，以提高控制器的整體運算效能與減少運算模組的數量。本論文所設計的適應性多模態類神經模糊晶片具有兩項顯著的特性：多模態架構及適應性學習功能。首先，控制器內部網路可透過架構參數(Si與Sj )的給定，依不同應用的需求，自我建構(self-constructed)為任意Si×Sj個IF-THEN法則的類神經模糊系統架構，以呈現網路多模態的特性。此外，晶片內部的適應性單元提供了參數學習與更新的機制，使控制器具有晶片學習(on-chip learning)的卓越能力。論文最後，我們以非線性倒車入庫平臺為受控體來驗證適應性類神經模糊控制器的正確性，經由軟體模擬與硬體驗證的結果，證實本論文所提出之適應性多模態類神經模糊晶片擁有良好的控制性能與架構彈性。由於硬體實現可彌補軟體在執行效能不足的缺點，並能將所設計的控制晶片應用於實際的硬體平台，所以本篇論文涵蓋了整個適應性類神經模糊控制器的軟硬體設計流程，理論與應用兩者俱佳。

　　The main focus of this thesis is on the chip design and implementation of an adaptive multimode neuro-fuzzy chip (AMNFC) by VLSI technology. The design concept of the AMNFC is based on high-level synthesis approach. That is, the signal flow and computation of the neuro-fuzzy system are mapped into a group of data-flow graphs (DFGs). Suitable scheduling and allocation algorithms are then developed for the DFGs to optimize the computation performance and resource utilization of the AMNFC. Two salient features of the AMNFC are multi-mode structure flexibility and on-chip learning capability. The multi-mode structure flexibility was controlled by two structure parameters (Si and Sj). That is, the AMNFC can be constructed into various network structures with Si�eSj IF-THEN rules according to the need of different applications. Moreover, the on-chip learning capability enables the AMNFC to fine-tune the overall control performance through its internal adaptive function unit. Finally, the AMNFC was used to control a car-backing system to validate its effectiveness. The simulation results of both software and hardware show that the AMNFC are able to control the system using different neuro-fuzzy structures with excellent performance. The advantage of the AMNFC hardware implementation is to accelerate the execution speed of neuro-fuzzy systems in software and to directly apply for real-world applications.

目錄

中文摘要 i
英文摘要 ii
目錄 iii
表目錄 v
圖目錄 vi
第 1 章 緒論 1-1
1.1 研究背景與動機 1-1
1.2 文獻探討 1-1
1.2.1 類比晶片設計 1-2
1.2.2 數位晶片設計 1-3
1.2.3 混合類比數位設計型式 1-5
1.3 研究目的 1-7
1.4 論文架構 1-7
第 2 章 類神經模糊系統理論 2-1
2.1 前言 2-1
2.2 模糊邏輯控制 2-1
2.2.1 模糊化介面 2-3
2.2.2 模糊知識庫 2-3
2.2.3 推論引撆 2-3
2.2.4 解模糊化介面 2-3
2.3 類神經網路 2-4
2.3.1 神經元的生物模型 2-4
2.3.2 類神經網路模型 2-5
2.3.3 倒傳遞演算法 2-7
2.4 類神經模糊系統 2-9
2.5 適應性類神經模糊控制器 2-10
2.5.1 適應性類神經模糊控制器之設計 2-10
2.5.2 參數更新學習演算法 2-12
2.6 倒車最佳路徑規劃 2-13
第 3 章 控制器超大型積體電路設計 3-1
3.1 高階合成設計策略 3-1
3.1.1 資料流程圖 3.4
3.1.2 排程 3-5
3.1.3 配置 3-8
3.2 適應性多模態類神經模糊晶片架構與規格 3-10
3.2.1 前饋單元 3-11
3.2.2 適應性單元 3-18
3.2.3 暫存器陣列單元 3-23
3.2.4 記憶單元 3-23
3.2.5 控制單元 3-23
3.2.6 特殊用途運算模組介紹 3-25
第 4 章 軟體模擬與硬體驗證 4-1
4.1 倒車入庫系統介紹 4-1
4.2 軟體模擬 4-2
4.2.1 FLC應用於倒車平台 4-2
4.2.2 NFC (Neuro-Fuzzy Controller)與ANFC (Adaptive NFC) 4-3
4.2.3 軟體模擬結果 4-4
4.2.4 精簡架構ANFC 4-13
4.3 硬體驗證 4-16
4.3.1 硬體與平台簡介 4-16
4.3.2 硬體模擬結果 4-20
4.3.3 控制器運算效能與硬體資源分析 4-25
第 5 章 結論與未來工作 5-1
5.1 結論 5-1
5.2 未來工作 5-1
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