臺灣博碩士論文加值系統

本文以半導體末段製程之記憶體IC最終測試廠為研究對象，考量其主要生產特性，包含：訂單式代工服務、多產品等級、測試製程迴流、序列相關設置時間以及批次作業等特性。半導體最終測試廠最重視之營運目標為顧客滿意度，主要取決於訂單是否準時達交。因此，本文以最小化延遲工單數為衡量指標，構建一主生產排程規劃系統。
本文發展之模式分為三部份，首先針對規劃週期內之需求，以產能負荷平準化為原則，構建線性規劃模式，並將規劃週期內預定完成之產品數量指派予各機群。接著，以等候理論為基礎，根據前一階段規劃之各機群分配情況，預估各產品各等級之生產週期時間，並藉此估算值設定各工單之內部交期。最後以固定在製品投料法，考量各工單交期緊迫度及機群當時負荷狀況，設定現場投料及派工之準則。
透過粗略產能規劃階段均勻分配各機群之產能負荷，配合主生產排程階段之生產週期時間估算以及現場投料規劃，可迅速產生一生產排程。模擬結果顯示，經由以上三階段之生產規劃與控制流程，各工單之達交比率可以達到相當良好之成果。

This research consider the construction of master production planning system for the memory IC final testing process in wafer fabrication, which includes such properties as make-to-order OEM services, multiple-priority orders, reentrant flow in final testing process, sequence dependent setup time, and batch operation. The most important performance criteria for IC final testing factories relates to customer satisfaction, which is measured by the on- time delivery of orders. Consequently, this research aims to construct a master production planning system with the minimization of the number of delay orders.
The construction of master production planning system consists of three phases. First, according to the order demands in the planning horizon and the rule of balanced capacity loading, a linear programming model, developed in this research, is used to allocate the capacity of workstations to products. Second, based on the queuing theory and the allocation results in the first phase, estimates the production cycle time for all product type in all priorities. Furthermore, the estimated production cycle time will be regarded as the internal delivery due-date of lots. Finally, considering the priority of each lot and the capacity loading status of workstations, and according to constant WIP releasing, selects suitable releasing rules or dispatching rules in the shop floor.
The rough-cut capacity planning (RCCP) developed in the first phase balances the capacity loading of workstations. The master production planning (MPS) developed in the second phase determines the estimation of product cycle time. The three phases master production planning system generates a production schedule. The simulation results show that the three phases master production planning system performs well in the criteria of on- time delivery ratio.

摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 vii
表目錄 viii
符號一覽表 x
第一章 緒論 1
1.1 研究背景與動機 1
1.2 研究目的 2
1.3 研究範圍與限制 3
1.4 研究方法 4
第二章 文獻探討 6
2.1 IC最終測試廠的基本生產環境簡介 6
2.1.1 設備簡介 6
2.1.2 IC測試流程 7
2.1.3 現場特性 8
2.2 IC最終測試廠生產規劃所遭遇到之主要問題 11
2.2.1 序列相關設置時間[11] 12
2.2.2 平行機台問題 12
2.2.3 粗估產能規劃 14
2.2.4 週期時間估算 15
2.2.5 投料與派工法則 15
第三章 模式構建 16
3.1 問題定義與分析 16
3.1.1 現場生產特性 16
3.2 整體邏輯與架構 19
3.3 產能分配與生產週期時間估算 21
3.3.1 資料需求定義階段 21
3.3.2 在製品存貨佔用產能 23
3.3.3 測試機台粗略產能規劃 24
3.3.4 預燒機台粗略產能規劃 27
3.3.5 測試機台生產週期時間估算 29
3.3.5.1 序列相關設置時間估算 30
3.3.5.2 等候時間與實際加工時間 31
3.3.6 預燒機台生產週期時間估算 34
3.4 交期指定 38
3.4 投料規劃與派工法則 40
3.4.1 CONWIP在投料規劃之運用 42
3.4.1.1 投料機制 42
3.4.2 派工法則 42
第四章 實例驗證 44
4.1 前言 44
4.2 系統環境說明 44
4.3 輸出資訊與績效評估 48
4.3.1 測試機群與預燒機群負荷分配 48
4.3.2 生產週期時間之預測與分析 49
4.4 實驗設計與成果 54
第五章 結論與未來研究方向 59
5.1 結論 59
5.2 未來研究方向 60
參考文獻 61

1. Akkan, C., ” Finite-capacity scheduling-based planning for revenue-based capacity management,” European Journal of Operational Research Vol. 100, pp. 170-179, 1997
2. Azizoglu, M., and Kirca, O., ”On the minimization of total weighted flow time with identical and uniform parallel machines,” European Journal of Operational Research Vol, 113, pp. 91-100, 1999
3. Glassey, C. R., and Resende, M. G. C., “Cloased-loop Jop Shop Release Control for VLSI Circuit Manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 1, pp. 26-46, 1988.
4. Kovalyov, M. Y., and Shafransky, Y. M.,”Batch scheduling with deadlines on parallel machines: An NP-hard case,” Information Processing Letters, Vol. 64, pp. 69-74, 1997
5. Lee, Y. H., and Pinedo, M., ”Scheduling jobs on parallel machines with sequence-dependent setup times,” European Journal of Operation Research, Vol.100, pp. 464-474, 1997
6. Liu, W. P., Sidney, J. B., and van Vliet, A., ”Ordinal algorithms for parallel machine scheduling,” Operations Research Letters, Vol. 18, pp. 223-232, 1996
7. Lou, S. X. C., and Kager, P. W., “A Robust Production Control Policy for VLSI Wafer Fabrication,” IEEE Transactions on Semiconductor Manufacturing, Vol. 2, No. 4, pp. 159-164, 1989
8. Lu, S. C. H., Ramaswamy, D., and Kumar, P. R., “Efficient Scheduling Policies to Reduce Mean and Variance of Cycle-Time in Semiconductor Manufacturing Plants,” IEEE Transactions on Semiconductor Manufacturing, Vol. 7, No. 3, pp. 374-388, 1994
9. Mandel, M., and Mosheiov, G., ”Minimizing maximum earliness on parallel identical machines,“ Computers and Operations Research, Vol, 28, pp. 317-327, 2001
10. Morton, T. E., and Pentico, D. W., “Heuristic Scheduling System with Applications to Production Systems and Project Management,” 1993
11. Perry, C. N., and Uzsoy, R., “Reactive scheduling of a semiconductor testing facility,” Fifteenth IEEE/CHMT International, pp. 191 —194, 1993
12. Piersma, N., and van Dijk, W., ”a local search heuristic for unrelated parallel machine scheduling with efficient neighborhood search,” Mathematical and Computer Modeling, Vol.24, No9, pp. 11-19, 1996
13. Uzsoy, R., Church, L. K., and Ovacik, I. M., “Dispatching Rules For Semiconductor Testing Operations: A Computational Study,” Thirteenth IEEE/CHMT International, pp.272 —276, 1992
14. Weng, W. W., and Leachman, R. C., “An Improvement Methodology for Real-time Production Decision at Batch-process Workstations,” IEEE Transactions on Semiconductor Manufacturing, Vol. 6, No. 3, pp. 219-225, 1993.
15. Zijm, W. H. M., and Buitenhek, R., ”Capacity planning and lead time management,” International Journal of Production Economics, Vol. 46-47, pp. 165-179, 1996
16. 大野耐一， 「豐田生產方式與現場管理」，日本能率協會，中華企業管理發展中心，1981
17. 呂思賢， 「使用基因演算法配合其他啟發式演算法解決炙燒爐指派問題」，交通大學資管所碩士論文，2000
18. 李晉裕， 「半導體測試廠有限資源產能規劃研究」，中原大學工業工程學系碩士論文，2000
19. 黃宏文， 「The block-based cycle time estimation methodology for wafer fabrication factories」，國立交通大學工業工程與管理學系博士班，博士論文計劃書，1999
20. 黃宏文， 「具製程規格能力機台之負荷分配」，Journal of the Chinese Institute of Industrial Engineers, Vol 18, No. 4, pp.82-96, 2001
21. 蘇志浩， 「以限制驅導式為基之半導體最終測試廠短期生產排程模式」 ，國立清華大學工工所碩士論文，1999
22.蘇昱彰， 「新興晶圓代工廠生產規劃與排程系統之構建」 ，國立交通大學工工所碩士論文，1998