臺灣博碩士論文加值系統

摘要
近幾年可攜式之無線通訊裝置已普遍被市場所接受，對於低電壓、低功率消耗之產品需求亦日益增加。本論文是以CMOS 0.35 mm製程，設計並實現一低電壓射頻鎖相頻率合成器晶片，在晶片規格上，除參考市面上已有之鎖相頻率合成器晶片外，並特別改善預除器在低電壓環境下的可操作頻率。晶片之佈局後模擬(Post-Layout Simulation)結果顯示，在供應電壓為2.0 V時，最高可操作在766 MHz；若額定供應電壓為3.0 V，則最高工作頻率可達1.2 GHz。
本論文主要分為以下四個部分：第一部份為鎖相頻率合成器之概念與理論分析。第二部分為晶片內部組件之電路設計與佈局模擬，此部分整合了類比和數位電路。類比電路包含電流源，電流汞(Charge Pump)與內建環形壓控振盪器(Ring VCO)；數位電路包含移位暫存器、預除器、可程式除頻器和三態相位頻率偵測器(Tri-States PFD)。第三部分為射頻壓控振盪器之設計，在此使用虛擬接地觀念之迴授型分析方式，並舉例實際製作一2.4 GHz之壓控振盪器。第四部分為晶片內部各組件之量測，並配合外部之迴路濾波器和壓控振盪器，構成一完整的頻率合成器。

Abstract
Phase-locked loop (PLL) frequency synthesizers have been widely used in most communication systems. Low voltage, low power consumption, and high speed have become critical design issues. In this thesis, a PLL frequency synthesizer IC has been designed and implemented by 0.35 mm, one poly and four metals CMOS process. Post-layout simulation of the proposed chip shows the maximum operating frequency is 766 MHz with 2.0 V supply voltage, and 1.2 GHz with 3.0 V supply voltage.
In the thesis, firstly the concept and theoretical analysis of PLL frequency synthesizers are given. Secondly, design and layout of the proposed chip are discussed in detail. Thirdly, an alternative oscillator-analysis method (“transmission analysis with virtual ground”) is used for designing a voltage control oscillator (VCO). At the end of the thesis, a complete frequency synthesizer, based on the designed chip, loop filter, and VCO, is presented.

第一章 簡介……………………………………………………………1
第二章 系統架構………………………………………………………3
2-1 直接數位頻率合成器…………………………………3
2-2 鎖相迴路頻率合成器……………………………………4
2-2-1基本架構……………………………………………5
2-2-2鎖定範圍…………………………………………10
2-2-3鎖定過程……………………………………………13
第三章迴路組件之設計………………………………………………16
3-1 預除器…………………………………………………..16
3-1-1 電路架構………………………………………….17
3-1-2 佈局與模擬……………………………………….22
3-2 輸入資料暫存器與可程式除頻器……………………23
3-2-1 電路架構…………………………………………24
3-2-2 佈局與模擬………………………………………26
3-3 相位偵測器與電流汞………………………………27
3-3-1不同類型的相位偵測器……………………………29
3-3-2 死角範圍之改善…………………………………33
3-3-3 電路架構…………………………………………37
3-3-4 佈局與模擬………………………………………39
3-4 環形壓控振盪器………………………………………40
3-4-1 電路架構…………………………………………41
3-4-2 佈局與模擬……………………………………43
3-5 晶片擺設………………………………………………45
第四章 電壓控制振盪器………………………………………………49
4-1振盪器設計原理…………………………………………50
4-1-1 反射型振盪器……………………………………50
4-1-2 迴授型振盪器……………………………………52
4-1-3 諧振電路之設計………………………………….54
4-2 相位雜訊………………………………………………58
4-3電路設計與模擬…………………………………………59
4-3-1 線性分析………………………………………….60
4-3-2 非線性分析…………………………………….63
4-4 壓控振盪器實測………………………………………65
第五章 晶片量測……………………………………………………68
5-1 晶片量測………………………………………………68
5-1-1 預除器……………………………………………69
5-1-2 相位頻率偵測器…………………………………73
5-1-3 環形壓控振盪器…………………………………76
5-2頻率合成器整合…………………………………………78
第六章 討論與未來工作……………………………………………81
參考文獻………………………………………………………………82

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