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研究生:梁佑安
研究生(外文):Liang, Yu-An
論文名稱:應用於生醫植入晶片系統的全整合式金氧半多重低壓降穩壓器設計
論文名稱(外文):The Design of Fully-Integrated CMOS Multiple Low Dropout Regulators for Implantable Biomedical SoCs
指導教授:吳重雨
指導教授(外文):Wu, Chung-Yu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2011
畢業學年度:100
語文別:英文
論文頁數:97
中文關鍵詞:穩壓器
外文關鍵詞:Low Dropout RegulatorLDO
相關次數:
  • 被引用被引用:0
  • 點閱點閱:435
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  • 下載下載:47
  • 收藏至我的研究室書目清單書目收藏:0
在癲癇偵測與刺激的應用上,生醫元件必須要植入人體體內。為了能夠有效的縮小面積以及消除外部元件造成的寄生電感效應,系統所使用的低壓降穩壓器必須完全整合到晶片上。此外,對於一個由近場無線傳能的可植入的醫療SoC元件而言,單一個低壓降穩壓器供壓很難滿足所有類比、數位、以及參考電壓電路的需求。因此,我們設計、實作、並驗證了一個應用於SoC上的全互補式金氧半低壓降穩壓器設計方式,同時實現三個穩壓器將大於2V的輸入電壓轉換成1.8V的穩定直流輸出分別供壓於類比、數位、以及參考電壓。以上的三個輸出端的最大輸出電流分別為5mA、20mA、以及1.5mA。利用將穩壓器輸入連結到的一個操作在13.56MHz的由近場線圈供壓的全波互補式金氧半主動式整流器輸出端,我們成功的驗證透過近場無線傳能的方式,也能穩定的由穩壓器輸出穩定的直流電壓1.8V。而最終量測到的類比輸出電壓、數位輸出電壓、以及參考電壓輸出的漣波分別為3.6mVp-p、6.2mVp-p、以及0.7mVp-p。
For epilepsy detection and stimulation application, the medical device should be fully implantable. In order to minimize the area consumption and eliminate the negative effect of parasitic inductance, the LDO regulators should be fully-integrated without any external component. Moreover, in an implantable medical SoC powered by inductive link power supply, a single LDO is difficult to satisfy different performance requirements of analog, digital, and reference circuits. Therefore, a topology of LDO is designed, fabricated, and tested to realize three fully-integrated LDOs with 2V to 1.8V output voltages for analog, digital, and reference circuits. The maximum driving current capabilities are 5mA, 20mA and 1.5mA, respectively. By connecting the input voltage of the LDOs to a full-wave CMOS active rectifier which is operated at 13.56MHz and powered by near-field coils with an inductive link structure. The measured ripple voltages of analog output, digital output, and reference output are 3mVp-p, 6.2mVp-p, and 0.7mVp-p, respectively.
CHAPTER 1 INTRODUCTION 1
1.1 Background 1
1.2 Review on Low Dropout (LDO) Regulators 2
1.3 Motivation and Main Results 4
1.4 Thesis Organization 6
CHAPTER 2 CIRCUIT DESIGN AND SIMULATION RESULTS 10
2.1 Design Consideration 10
2.2 Replica-Biased Loop 13
2.3 LDO Regulator for Analog Circuits 14
2.3.1 Stability and Compensation Method 15
2.3.2 Line Regulation 20
2.4 LDO Regulator for Digital Circuits 23
2.4.1 Load Transient Response 23
2.4.2 Slew-Rate Enhancement Technique 26
2.5 LDO Regulator for Reference 27
2.6 Bandgap Reference 28
2.7 Simulation Results 29
CHAPTER 3 EXPERIMENTAL RESULTS 67
3.1 Chip Layout Descriptions 67
3.2 Measurement Setup 68
3.3 Experimental Results 70
3.4 Discussions 72
CHAPTER 4 CONCLUSIONS AND FUTURE WORK 92
4.1 Conclusions 92
4.2 Future Work 93
REFERENCES 95
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