臺灣博碩士論文加值系統

本論文提出一個操作在4 GHz、擁有10個相位輸出之全數位式鎖相迴路之單晶片系統設計。此鎖相迴路所運用之多重相位數位控制振盪器採用三態反向器組成的迴圈，以獲得高頻率輸出及寬範圍操作。所使用之時間數位轉換器重複利用振盪器的多相位輸出來對時間差值作取樣，因此可大幅減少面積消耗。並加入了一個時間放大器，來增加時間數位轉換器的解析度。另外，藉由一個頻率偵測器，加速數位控制振盪器在選擇頻段下的運作，增加鎖相迴路中頻率追鎖的速度。因此，本鎖相迴路能滿足可攜式電子產品應用之需求。
本論文之全數位式鎖相迴路使用TSMC 90 nm 1P9M CMOS製程實現晶片，其操作頻率範圍可從3 GHz到4.2 GHz。電路在操作頻率為4 GHz時，功率消耗為52 mW，而輸出訊號之最大峰對峰值時間抖動量為12.14 ps (4.86 %)，方均根抖動量為1.44 ps。整體晶片面積為510 × 590 um2，核心電路的面積為140 × 220 um2。

A 4-GHz 10-phase all digital phase-locked loop (ADPLL) is proposed for system-on-chip (SoC) systems. The proposed multiphase digital controlled oscillator (MP-DCO) adopts the tri-state inverter loop scheme to obtain the higher operating frequency and wide operation range. The MP-DCO outputs are used to be Time-to-digital Converter (TDC) sampled clock and sample the time difference. Therefore, the reused MP-DCO output can reduce the area cost of the TDC. Time amplifier (TA) can extend the timing resolution of the TDC. The frequency acquisition can achieve the fast locking time using frequency detector (FD) and multi-band operation range of the MP-DCO. Thus, this clock generator is suitable for portable products and mobile applications.
The experimental chip was fabricated by TSMC 90 nm 1P9M CMOS process. The measurement results show that the operation range is from 3 GHz to 4.2 GHz, and the power consumption is 52 mW at 4 GHz. The peak-to-peak jitter and RMS jitter are 12.14 ps and 1.44 ps at 4 GHz, respectively. The whole chip area is 510 × 590 um2, and the core area is 140 × 220 um2.

第1章 緒論 1
1.1 研究動機 1
1.2 研究目的及其應用 2
1.3 論文架構 3
第2章 全數位式鎖相迴路先前技術探討 5
2.1 鎖相迴路種類簡介 5
2.2 全數位式鎖相迴路架構探討 6
2.2.1 低時脈抖動之全數位式鎖相迴路[1] 6
2.2.2 可抵抗PVT變異之全數位式鎖相迴路[2] 8
2.2.3 快速鎖定之數位式鎖相迴路[3] 9
2.2.4 低相位雜訊之數位式鎖相迴路[4] 11
2.2.5 免校正之數位式鎖相迴路[5] 12
2.2.6 各種鎖相迴路架構規格比較 14
2.3 本論文預計規格 16
第3章 多重相位數位控制振盪器並應用於時間數位轉換器與頻率偵測器 17
3.1 設計概念 17
3.2 多重相位數位控制振盪器 (MP-DCO) 18
3.2.1 多重相位數位控制振盪器公式探討[6] 18
3.2.2 多重相位數位控制振盪器架構 20
3.2.3 多重相位數位控制振盪器模擬結果 23
3.2.4 多重相位數位控制振盪器佈局考量 25
3.3 時間數位轉換器(TDC) 27
3.3.1 時間數位轉換器架構 27
3.3.2 時間數位轉換器模擬結果 32
3.3.3 時間數位轉換器之位元數探討 35
3.4 頻率偵測器(FD) 36
3.4.1 頻率偵測器架構 36
3.4.2 頻率偵測器模擬結果 38
第4章 全數位式鎖相迴路架構分析與子電路介紹 41
4.1 電路架構與操作 41
4.2 鎖相迴路系統分析[8] 43
4.2.1 全數位式鎖相迴路之S-domain分析 43
4.2.2 電荷幫浦鎖相迴路之S-domain分析 44
4.2.3 計算數位迴路濾波器之參數 45
4.3 全數位式鎖相迴路之子電路設計 48
4.3.1 相位頻率偵測器 48
4.3.2 數位迴路濾波器 50
第5章 電路模擬與晶片量測結果 53
5.1 設計流程 53
5.2 佈局前電路模擬 53
5.3 電路佈局與佈局後電路模擬 55
5.4 晶片照相與量測環境設定 58
5.5 量測結果 60
5.6 規格比較 64
第6章 結論與未來研究方向 67
6.1 結論 67
6.2 未來研究方向 67
參考文獻 69

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