臺灣博碩士論文加值系統

SAR ADC的解析度主要受限於製程製作出的電容比例是否準確。本論文提出一種適用於全差動SAR ADC的混和訊號式校正方式。對於一個由已知比例關係之方式所構成的待校電容陣列，我們可以使用此演算法去找出該陣列中各個電容因製程變異而產生的誤差量，並將之數位化後儲存。然後，在SAR ADC進行轉換的同時補償每次DAC轉換所產生的誤差，如此便可提升該SAR ADC的解析度。
本論文提出之校正方式，不論電容因製程的非理想性導致其值比標準值高或低，都有辦法做到誤差計算與補償，並且使比較器的設計難度降低，有效的提升了SA ADC的有效位元數。
模擬結果顯示，靜態參數的表現上校正前INL=-11/+11LSB，校正後INL=-0.9/+0.9LSB，動態參數的表現上，校正前SNDR=51.7dB，ENOB=8.3bits，校正後peak SNDR=71.6dB，ENOB=11.6bits，可大幅改善因電容不匹配所造成的非線性。實作晶片量測結果顯示，未啟動校正機制時，當取樣頻率為10M S/s時，peak SNDR=53.3dB，ENOB=8.6bits，而校正後之peak SNDR=53.3dB，ENOB=8.6bits。雖然電路實現的量測結果顯示此校正法有未臻完美之處，但若我們能校正segmented架構中main DAC與sub DAC間的匹配度，將會使此演算法的可應用範圍大大提升。

It is the mismatched capacitors due to process variation that limit the resolution of a conventional capacitive SAR ADC. To address this issue, this thesis proposes a mixed-signal calibration scheme for the fully differential SAR ADC. The proposed calibration scheme first estimates the ratio errors of the capacitors under calibration in the binary weighted capacitor array. Then, the errors will be digitized and stored. When the SAR ADC operates in the normal conversion, the calibration scheme will compensate the errors caused by the DAC in an analog way. The calibration scheme proposed in this thesis is able to calibrate the ratio errors of the capacitors, no matter the ratio error is positive or negative. With the proposed calibration scheme, the effective number of bits of the SAR ADC can be enhanced.
Simulation results show that the INL values are improved from -11~+11 LSB to -0.9~+0.9 LSB after calibration, and the SNDR and ENOB values are enhanced from 51.7dB and 8.3bits to 71.6dB and 11.6bits after calibration. The results show that the ADC’s performance can be significantly improved with the proposed calibration scheme.
We implemented a 12-bit 1.8V SAR ADC with the proposed calibration scheme in TSMC 0.18µm 1P6M CMOS process. Measurement results show that the SAR ADC achieves SNDR of 53.3dB and ENOB of 8.6 bits at 10 MS/s before calibration. The ADC consumes 5.94mW at 1.8-V.
The measurement results show this calibration method can be improved. The main issue is the mismatch between the main DAC and the sub DAC in the segmented structure. It is our future work to address this issue.

摘要 I
Abstract III
誌謝 V
目錄 VI
圖目錄 VIII
表目錄 XI
第一章 緒論 1
1.1 研究背景 1
1.2 SA ADC介紹 2
1.3 傳統單端輸入之SA ADC 4
1.4 改良型單端輸入之SA ADC 5
1.5 雙端輸入之SA ADC(一) 6
1.6 雙端輸入之SA ADC(二) 8
1.7 研究動機與目的 10
1.8 論文章節組織及研究方法 11
第二章 具有自我校正功能之SA ADC介紹 13
2.1 應用於SA ADC之由高至低式校正演算法 13
2.2 應用於SA ADC之由低至高式校正演算法 21
2.3 應用於SA ADC之全數位式校正演算法 26
2.4 應用於SA ADC之LMS式校正演算法 34
2.5 結論 35
第三章 提出之應用於全差動SA ADC的校正演算法 37
3.1 整體電路架構 37
3.2 所提出之全差動連續近似開關切換方法 38
3.3 SA ADC裡的誤差來源 45
3.4 加入校正演算法的電路動作流程與假設 46
3.5 所提出之誤差估測模式 49
3.5.1計算待校電容陣列中MSB電容誤差之方法 50
3.5.2計算待校電容陣列中MSB-1電容誤差之方法 55
3.6 所提出之具有誤差補償的正常轉換模式 60
3.7 偏移量對此校正演算法的影響 61
3.8 以電路之行為模型驗證所提出之演算法 61
3.8.1範例一：當MSB電容為正向誤差且MSB-1電容為負向誤差 62
3.8.2範例二：當MSB電容為負向誤差且MSB-1電容為正向誤差 65
3.8.3範例三：最大可校正之常態分布的亂數誤差於所有DAC 68
3.9 與先前所提出之校正方法相比較 72
第四章 具校正功能之12位元SA ADC設計 74
4.1 提出之SA ADC架構 74
4.2 取樣開關（Sampling switches） 74
4.3 具有偏移量補償功能的比較器級 79
4.3.1 前置放大器（Pre-Amplifier） 82
4.3.2 Regenerative latch 83
4.4 數位類比轉換器（Digital to Analog Converter） 84
4.4.1 加入校正用的電容與寄生電容之影響 89
4.5 提出之SA ADC數位電路設計 92
4.6 ADC佈局圖 94
4.7 電路模擬與驗證 96
4.8 Hardware Overhead 101
第五章 量測結果與性能分析 103
5.1 量測環境設定與晶片照 103
5.2 未執行校正功能時的測量結果 105
5.3 執行校正功能的測量結果 110
5.4 ADC之測量結果分析 112
第六章 結論與未來發展 120
6.1 結論 120
6.2 未來發展與待改進之處 120
參考文獻 122

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