臺灣博碩士論文加值系統

　　本次研究探索了兩種高耐壓並且能和雙極性電晶體或金氧半電晶體整合在一起的功率元件：降低表面電場之側向擴散型金氧半電晶體和三元降低表面電場之側向擴散型金氧半電晶體。
　　降低表面電場之側向擴散型金氧半電晶體主要的優點有二，第一，它具有高度的整合能力；第二，它在提供高耐壓的同時也能擁有一個很低的導通阻抗。製作這種元件的主要關鍵是精確的控制耐壓區內的摻雜量，在不影響導通阻抗的情況下，大量提昇其崩潰電壓。在本篇論文內，我們對這種元件有一詳細的研究與探討。
　　近年來，一種新的耐壓結構被發明並製作出來，這種結構稱為重疊介面結構或是多重降低表面電場結構。它的主要特色是其摻雜溶度不會受其耐壓的影響，因此，在提供高耐壓的同時，這種結構尚保有一個很高的摻雜溶度，所以它的導通阻抗比起一般功率元件低很多。雖然這種結構已成功的嵌入於垂直式雙擴散金氧半電晶體以及絕緣層矽晶片上的降低表面電場之側向擴散型金氧半電晶體內，但是，少有研究是探索這種結構在一般矽晶片上的功效的。本次研究首次探索三元降低表面電場之側向擴散型金氧半電晶體在矽晶片上的性能。雖然因為製程設計上的不當與製程本身的限制，元件特性並未如預期中的好，但是這種元件一些特有的性質依然在本篇論文內完全呈現出來。

Two topics of the reduced-surface-field (RESURF) lateral-diffusion MOSFETs (LDMOS) and the three-dimensional (3D) RESURF LDMOS are studied in the thesis. These devices can be easily integrated with bipolar or MOS transistors due to their planar structures. Moreover, the process is compatible with the CMOS or the BiCMOS process.
The prime merits of the RESURF LDMOS are the high integration ability and the high breakdown voltage (BV) with a low on-resistance (Ron). The key for the device is to control the dose of the drift region precisely. When the RESURF action takes place, the BV is increased greatly with little degradation of the Ron.
In recent years, an innovative structure, called the super-junction or the multi-resurf structure, was invented. The out-standing feature of the structure is that the structure maintain a high doping concentration at high-voltage ratings, and hence a very small Ron. Although the structure has been implemented into the vertical double-diffusion MOSFETs (VDMOS) and onto the silicon-on-insulator (SOI) wafer, few researches were focused on that on the bulk-Si wafer. We first investigate the 3D RESURF LDMOS on the bulk-Si wafer in the study. Though the performance is not as good as expected because of the improper process design and the constraints of the process in the laboratory, some special features of the device are still presented in the thesis.

Chapter 1 Introduction
1.1 Overview of RESURF LDMOS
1.2 Overview of 3D RESURF LDMOS
1.3 Motivation
1.4 Thesis Outline
Chapter 2 RESURF LDMOS
2.1 Introduction
2.2 Mechanism of RESURF Principle
2.3 Simulation of RESURF LDMOS
2.3-1 Breakdown Voltage and Specific On-resistance
2.3-2 Safe-operation Area
2.4 Experimental Results of RESURF LDMOS
2.4-1 The Experimental Performance
2.4-2 Comparison between Experimental and Simulated Results
2-5 Summary
Chapter 3 3D RESURF LDMOS
3.1 Introduction
3.2 Overview of The Super-junction Structure and 3D RESURF LDMOS
3.2-1 The Super-junction Structure and COOLMOS
3.2-2 3D RESURF LDMOS
3.3 The Evaluation and Simulation of 3D RESURF LDMOS on The Bulk-Si Wafer
3.3-1 The Evaluation of 3D RESURF LDMOS on The Bulk-Si Wafer
3.3-2 Simulation of 3D RESURF LDMOS on The Bulk-Si Wafer
3.4 Experimental Results of 3D RESURF LDMOS on The Bulk-Si Wafer
3.4-1 Experimental Results
3.4-2 Comparison between 3D RESURF LDMOS and RESURF LDMOS
3.5 Summary
Chapter 4 Conclusion
References
Chapter 1
Chapter 2
Chapter 3

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