臺灣博碩士論文加值系統

本論文中利用TSMC 0.35-um 2P4M mixed signal的製程來實現一個12位元高速電流式數位類比轉換器，其取樣頻率為100 MHz，此電流式數位類比轉換器是利用分段電流模式(segmented current mode)的架構來實現，此架構由七個高有效位元(7 MSBs)轉換成127個相同的電流源和五個低有效位元(5 LSBs)轉換成二進位加權方式的電流源所組成，利用此架構可改善數位類比轉換器的微分非線性誤差(DNL)、突波(glitch)和確保電路單調性。
在電路模擬方面，我們利用HSPICE來進行模擬，對於12位元 100 MHz電流式數位類比轉換器的模擬結果如下：積分非線性誤差(INL)<±0.3 LSB，微分非線性誤差(DNL)<±0.25 LSB，穩定時間(settling time)等於9 ns，突波為5.8 pV-s。當輸入頻率為1 MHz與49 MHz之正弦波時，無突波動態範圍(SFDR)分別為80 dB與67 dB，電路的消耗功率為127 mW。
在量測方面，對於取樣頻率為100 MHz之數位類比轉換器量測結果為積分非線性誤差(INL)<±0.6 LSB，微分非線性誤差(DNL)<±0.4 LSB，穩定時間(settling time)等於10 ns，突波為25 pV-s。當輸入頻率為200 kHz與5 MHz之正弦波時無突波動態範圍(SFDR)分別為70.3 dB與63.51 dB，電路的消耗功率為142 mW。

In this thesis, we realize a 12-bit 100 MHz current-steering digital-to-analog converter (DAC) in TSMC 0.35-um 2P4M mixed signal process technology. The DAC adopts the segmented architecture which comprises a segment of 7-bit into 127 equally weighted current sources in the MSB and a segment of 5-bit binary-weighted current sources in the LSB. The performance of differential nonlinearity error (DNL), glitch and monotonic of DAC can be improved by this architecture.
The DAC is simulated by HSPICE using TSMC 0.35-um 2P4M mixed signal process technology. The proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.3 LSB, DNL is less than 0.25 LSB, settling time is 9 ns, and glitch is 5.8 pV-s. For 1MHz sine wave input and 100 MHz sampling rate, the SFDR is 80 dB, and for 49MHz sine wave input and 100 MHz sampling rate, the SFDR is 67 dB. The power consumption is 127 mW at the maximum conversion rate.
The real world measurement results show that the proposed DAC has the following performances：The sampling rate of DAC is 100 MHz, INL is less than 0.6 LSB, DNL is less than 0.4 LSB, settling time is 10 ns, and glitch energy is 25 pV-s. For 200 kHz sine wave input and 100 MHz sampling rate, the measured SFDR is 70.3 dB, and for 5 MHz sine wave input and 100 MHz sampling rate, the measured SFDR is 63.51 dB. The measured power consumption is 142 mW at the maximum conversion rate.

中文摘要 i
英文摘要 iii
致謝 v
目錄 vi
表目錄 viii
圖目錄 ix
第一章 簡介 1
1.1動機 1
1.2論文結構 2
第二章　數位類比轉換器的基本原理 4
2.1簡介 4
2.2理想數位類比轉換器 5
2.3數位類比轉換器之特性 7
2.3.1靜態參數 7
2.3.2動態參數 12
2.3.3轉換參數 15
2.4數位類比轉換器之架構簡介 17
2.4.1解碼器架構 17
2.4.2二進位加權架構 19
2.4.3熱碼架構 23
2.4.4混合式架構 25
2.5結論 26
第三章 12位元100 MHz電流模式數位類比轉換器 27
3.1簡介 27
3.2架構簡介 27
3.2.1D-Latch 30
3.2.2熱碼解碼器 32
3.2.3電流單元 36
3.2.4電流源偏壓電路 46
3.2.5時脈樹和緩衝器 50
3.3佈局 51
3.4模擬結果 52
3.5結論 56
第四章 量測結果 57
4.1簡介 57
4.2測試方法 57
4.3量測結果 58
第五章 結論與未來工作 70
5.1結論 70
5.2未來工作 71
參考文獻 72
附錄一 理想ADC之MATLAB程式 77
附錄二 SFDR之MATLAB程式 80
附錄三 pattern generator之MATLAB程式 82
附錄四 RF transformer(T1-1T-X65)規格 85
附錄五 發表論文 86
自傳 87

[1]A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert, W. Sansen. “A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A Converter,” IEEE J. Solid-State Circuit, vol. 36, pp. 315-324, MarKevin O’Sullivan, Chris Gorman, Michael Hennessy, and Vincent Callaghan, “A 12-bit 320-Msample/s Current-Steering CMOS D/A Converter in 0.44 mm2,” IEEE J. Solid-State Circuit, vol. 39, no. 7, March 2001
[3]J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-bit intrinsic accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuit, vol. 33, pp. 1959-1969, Dec. 1998.
[4]John Hyde, Todd Humes, Chris Diorio, Mike Thomas, and Miguel Figueroa, “ A 300-MS/s 14-bit Digital-to-Analog Converter in Logic CMOS, “IEEE J. Solid-State Circuit, vol. 38, NO. 5, May 2003.
[5]Shu-Tuan Chin, and Chung-Yu Wu, “ A 10-b 125-MHz CMOS Digital-to-Analog Converter (DAC) with Threshold-Voltage Compensated Current Sources,” IEEE J. Solid-State Circuit, vol. 29, no. 11, November 1994.
[6]C. H. Lin and K. Bult, “A 10-b, 500-Msample/s CMOS DAC in 0.6mm2,” IEEE J. Solid-State Circuit, vol. 33, pp. 1948-1958, Dec. 1998.
[7]D. Wouter J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, “A Self-Calibration Technique for Monolithic High-Resolution D/A Converters,” IEEE J. Solid-State Circuit, vol. 24, pp. 1517-1522, Dec. 1989.
[8]G. A. M. Van der Plas, J. Vandenbussche, W. Sansen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. Solid-State Circuit, vol. 34, pp. 1708-1718, Dec. 1999.
[9]A. R. Bugeja, B. S. Song, P. L. Rakers, and S. F. Gillig, “A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance,” IEEE J. Solid-State Circuit, vol. 34, pp. 1719-1732, Dec. 1999.
[10]A. R. Bugeja, and B. S. Song, “A Self-Trimming 14-b 100-MS/s CMOS DAC,” IEEE J. Solid-State Circuit, vol. 35, pp. 1841-1852, Dec. 2000.
[11]P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design, Oxford, New York, 2002
[12]R. Gregorian, An Introduction to Mixed-Signal IC Test and Measurement, Oxford, New York, 2001.
[13]D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997.
[14]J. Bastos, M. Steyaert, B. Graindourze, and W. Sansen, “Matching for MOS Transistors with Different Layout Styles,” IEEE International Conference on Microelectronic Test Structures, vol. 9, pp. 17-18, March 1996.
[15]Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-bandwidth limitation for high-speed high-resolution current-steering CMOS D/A converter,” in Proc IEEE Int. Conf. Electronics, Circuits and System (ICESS), pp. 1193-1196, Sept. 1999.
[16]J. Bastor, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-bit intrinsic accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuit, vol. 33, pp. 1959-1969, Dec. 1998.
[17]M. Gustavsson, J. J. Wilner and N. N. Tan, CMOS Data Converter For Communication, Kluwer Academic Publishers, Boston, 2000.
[18]T. Miki, Y. Nakamura et al., “An 80 MHz 8-bit CMOS D/A converter,” IEEE J. Solid-State Circuit, vol. 21, pp. 983-988, DEC. 1986.
[19]J. Bastos, M. Steyaert, and W. Sansen, “A high yield 12-bit 250-MS/s CMOS D/A converter,” in Proc. IEEE 1996 CICC, May 1996, pp. 413-434
[20]A. Van den Bosch, M. Borremans et al., “A 12-bit 200-MHz low glitch CMOS D/A converter,” in IEEE 1998 Custom Integrated Circuit Conf. (CICC), pp. 249-252, May 1998.
[21]B. J. Tesch and J. C. Garcia, “A Low Glitch 14-b 100-MHz D/A Converter,” IEEE J. Solid-State Circuit, vol. 32, pp. 1465-1469, Sep. 1997.
[22]D. Mercer, “A 16-b D/A Converter with increased spurious free dynamic range,” IEEE J. Solid-State Circuit, vol. 29, no. 10, pp. 1180-1181, Oct. 1994.
[23]C. H. Lin and K. Bult, “A 10-b, 250-Msample/s CMOS DAC in 1mm2,” in Proc. 1998 Int. Solid-State Circuit Conf. (ISSCC), pp. 214-215, Feb. 1998.
[24]A. Torralba, R. G. Carvajal, J. Ramirez - Angulo and F. Munoz, “Output stage for low supply voltage, high-performance CMOS current mirrors,” Electron Letter, vol. 38, no. 24, Nov. 2002.
[25]J. Vandenbussche, G. Van der Plas, et al., “Systematic Design of High-Accuracy Current-Steering D/A Converter Macrocells for integrated VLSI System,” IEEE Trans. Circuit and System II, vol. 48, no. 3, March 2001.
[26]Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b 70-MS/s CMOS D/A Converter,” IEEE J. Solid State Circuit, vol. 26, pp. 637-642, April 1991.
[27]C. Bastiaansen, D. Groeneveld, H. Schouwenarrs, and H. Termeer, “A 10-b 40-MHz 0.8-um CMOS current-output D/A converter,” IEEE J. Solid-State Circuit, vol. 26, no. 7, pp. 917-921, July 1991.
[28]A. Cremonesi, F. Maloberti, and G. Polito, “A 100-MHz CMOS DAC for video-graphic system,” IEEE J. Solid-State Circuit, vol. 24, no. 3, pp. 635-639, June 1989.
[29]J. Fournier and P. Senn, “A 130 MHz 8-bit CMOS video DAC for HDTV applications,” IEEE J. Solid-State Circuit, vol. 29, no. 10, pp. 1180-1181, Oct. 1994.
[30]J. Jacob Wikner and Nianxiong Tan, “Modeling of CMOS Digital-to-Analog Converter for Telecommunication,” IEEE J. Solid State Circuit, vol. 46, no. 5, May 1999.
[31]K. Martin, Digital Integrated Circuit Design, Oxford, New York, 2000.
[32]Behzad Razavi, Design of Analog CMOS Integrated Circuit, McGraw-Hill, Boston, 2001.
[33]Christopher Saint and Judy Saint, IC Mask Design, McGraw-Hill, Boston, 2003.
[34]M. J. M. Pelgrom, A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE J. Solid State Circuit, vol. 24, pp. 1433-1440, Oct. 1989.
[35]Kazuhisa Nojima and Yuji Gendai, “An 8-b 800-MHz DAC,” IEEE J. Solid State Circuit, vol. 25, no. 6, Dec. 1990.
[36]Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Oxford, New York, 2002.
[37]K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copland, “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-State Circuits, vol. SC-21, Dec 1986, pp. 1057-1066.