臺灣博碩士論文加值系統

本論文提出一個低頻寬的二階層的跨畫面/跨視角的快取記憶體架構，且支援可彈性擴充視角的多視角視訊解碼器，可彈性擴充視角可使兩個解碼器平行的解碼多視角視訊的影片。在本論文中第一階層的快取記憶體架構是被設計用在單一視訊解碼器核心，我們的第一階層快取記憶體架構在解碼時可以節省移動預測所需的頻寬，在P畫面平均可以節省百分之四十的頻寬，在B畫面平均可以節省百分之六十的頻寬，為了更進一步，我們也提出了第二階層的快取記憶體架構，第二層的快取記憶體架構適用於當我們有多顆解碼核心在同時進行視角與視角之間的移動預測時，解碼核心可以藉由我們的快取記憶體架構去重複利用相同的參考資料，我們的第二階層快取記憶體架構可以進一步節省大約百分之三十的頻寬。藉由結合兩者我們可以節省百分之八十的頻寬消耗，使之可以達到HD1080兩個視角視訊的即時解碼。

This thesis presents a low-bandwidth two-level inter-frame/inter-view cache architecture for a view scalable multi-view video decoder, which adopts two decoder cores to decode multi-view videos in parallel. The first level inter-frame cache is developed for the single video decoder core, which is able to reduce 40% bandwidth in P frame and 60% in B frame in doing inter-frame prediction in average. Moreover, we develop the second level inter-view cache architecture to reuse the same reference data for doing inter-view prediction among different decoder cores, which can further reduce 30% bandwidth. By adopting the proposed two-level cache architecture for doing inter-frame/inter-view prediction, we can reduce 80% bandwidth through a view scalable multi-view video decoder implementation, which achieves real-time HD1080 dual-view video decoding.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 4
1.3 Thesis Organization 5
Chapter 2 Previous Works 6
2.1 Overview of H.264/AVC Decoder 6
2.2 the Overviews of Multi-Views Video Coding 9
2.3 The Existing Cache Architecture Used For H.264 and MVC 15
Chapter 3 Proposed Design Architecture 21
3.1.1 Inter-frame-Cache in Software analysis 21
3.1.2 Cache update mechanism 27
3.1.3 Inter-Frame Cache In Hardware Implementation 30
3.1.4 Pipeline Cache Architecture 38
3.2 Inter-View Cache analysis 41
Chapter 4 Performance Result and Performance Comparison 51
4.1.1 Performance Result of Inter-frame Cache 51
4.1.2 Performance Result of Inter-views-Cache 55
4.2 Performance Comparison 56
Chapter 5 Conclusion 59
Reference 60

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