臺灣博碩士論文加值系統

在本文中，我們針對傳統之一般目的計算機（general purpose machine ）及特定目
的之超大型積體電路（special purpose VLSI circuit）兩種截然不同的設計環境，
討論各種離散富氏轉換及數位迴旋之快速計算法則與運算結構。我們成功的導出了一
些有關離散富氏轉換與數位迴旋計算的有效方法及硬體結構。此外，我們也成功的擴
展了一些現存數位信號處理計算法則之應用範圍。
最後我們提出了一種分散式超大型積體電路連結網路模式用以實現上述計算法則與運
算結構。

TABLE OF CONTENTS
Chapter I： Introduction
1.1 Introduction
1.2 Thesis Summary
1.3 Contributions
I.4 References for Chapter I
Chapter II： General Considerations And A Review Of The Typical Fast Algorithms For Digital Signal Processing
2.1 Introduction
2.2 Fast Algorithms For Discrete Fourier Transforms
2.3 Fast Algorithms For Digital Convolutions In A Finite Integer Rings or Fields : Number Theoretic Transforms
2.4 Fast Algorithms For Digital Convolutions In A Polynomial Ring : Polynomial Transforms
2.5 Appendix ; A Simple Review Of The Winograd Fourier Transform Algorithm
2.6 References for Chapter II
Chapter III: Fast Biased Polynomial Transforms
3.1 Introduction
3.2 Fast Biased Polynomial Transforms For 2D Convolutions
3.3 Fast Biased Polynomial Transforms For 2D Prime Length Discrete Fourier Transforms
3.4 Hardware Considerations for The Realization of FBPTs
3.5 Discussions And Conclusions
3.6 Appendix i Short Length Winograd - Liked FBPT Algorithms
3.7 References for Chapter III
Chapter IV： Fast P-adic Number Transforms For Exact Convolution Of Rational Sequences
4.1 Introduction
4.2 P-adic Number Transforms And The Finite Segmented Hensel Code Planes
4.3 P-adic Number Transforms With Length Extension
4.4 Exact Computation Of Digital Convolution Of Rational Sequences By Polynomial Transforms In the Hensel Code Plane
4.5 Miscellaneous Discussions
4.6 Conclusions
4.7 Appendix
4.8 References for Chapter IV
Chapter V：Considerations In The Development Of VLSI Algorithms For Signal Processing
5.1 Introduction
5.2 Functional and Structural Modularity
5.3 Geometry of Interconnections
5.4 Concurrent Processing
5.5 Finite Wordlength Effects
5.6 Conclusions
5.7 References for Chapter V
Chapter VI Systolic Architecture / Algorithm For DFT And Digital Convolution
6.1 Introduction
6.2 Systolic Impementations For Discrete Fourier Transforms
6.3 Parallel Architectures For Computing Digital Convolutions
6.4 A New Interpretation of Multidimensional Digital Convolutions
6.5 Conclusions
6.6 References for Chapter VI
Chapter VII : A VLSI Cell-Based Interconnection Network
7.1 Introduction
7.2 Modelling and Complexity Analysis
7.3 Systematic Construction of A Cell-Based VLSI Interconnection Network
7.4 Applications
7.5 Discussions And Conclusions
7.6 References for Chapter VII
Chapter VIII: Conclusions And Future Research Work
8.1 Thesis Conclusions
8.2 Futrre Research Works
8.3 References for Chapter VIII
acknowledgements
中文摘要
英文摘要
圖目錄
表目錄