臺灣博碩士論文加值系統

超大型積體電路(ULSI)在高電晶體容量與運算速度的需求快速增加下，使得元件尺寸縮小，內連線尺寸也必須相對縮小。因此晶片的運作速度不再受限於元件的操作速度，而是取決於其導線間之訊號傳遞速度。因此，當導線的線寬逐漸縮小後，晶片的效能將主要受限於後段製程的內連線延遲與耗損。為了改善這些問題，使用低介電常數材料作為導線間的介電層為必要選擇。
　　本研究中所使用的低介電常數材料為奈米孔洞二氧化矽薄膜。然而，由於高孔隙率的關係，衍生出許多製程上的問題，增加實際導入生產製程上的困難，如吸水性、蝕刻氣體滲入孔洞等。有鑑於此，我們提出蝕刻後移除模板分子的概念來改善上述之問題，並於蝕刻製程完成後，採用O3 氧化法同時進行模板分子及光阻移除，而達到製程簡化的效果。於研究中，我們已成功地利用模板分子於蝕刻後才進行臭氧煅燒移除的方式來改善原先於蝕刻製程上所衍生出薄膜性質劣化的問題。
　　另外，本研究亦探討奈米孔洞二氧化矽薄膜的乾蝕刻特性，並進行溝渠引洞結構圖案之蝕刻。藉由改變蝕刻條件，如反應氣體、F/C比例、電漿功率、偏壓(bias)以及系統壓力等，來了解其對於奈米孔洞薄膜的影響。於研究中，我們發現奈米孔洞二氧化矽薄膜之蝕刻率會隨著電漿功率、偏壓以及F/C比例的增加而增加。另一方面，經HMDS疏水化改質處理的薄膜，其蝕刻率會比未經處理的薄膜慢，顯示蝕刻速率與薄膜本身的碳含量有很大的關係。

Due to the rapid increase in transistor density and the operation speed of an IC chip, the ultralarge-scale integrated circuit (ULSI) has an urgent demand for scaling down the device size, and thus the dimension of the interconnect accordingly. Consequently, the performance of the chip is no longer solely limited by the operation speed of the transistors, but also depends on the speed of the signal propagating through the interconnect. As the line width of the metal interconnect reduces, the performance of an IC chip can be degraded by interconnect RC delay and power consumption. In order to alleviate the problems, low dielectric constant (k) materials are used to replace the conventional intermetal dielectric (IMD), SiO2.
In this thesis, low-k nanoporous silica dielectrics used as the IMD material for ULSI applications is reported. Because of the high porosity, implementation of the nanoporous silica in the IC process will result in many integration problems, such as water uptake on the pore surface, impurity permeation thorough the pores, mechanical deficiency, etc. In this work, we propose a post-etch pore formation method to mitigate impurity diffusion in the nanoporous dielectric during the etch process and improve hydrophobicity of the low-k dielectric. Instead of conventional way to remove the organic template from the silica matrix by calcination before IMD pattering, nanopores of the low-k silica dielectric are formed in-situ as the photoresist is stripped by ozone ashing after the reactive-ion-etch process.
In the study, we compared the etch characteristics of HMDS treated nanoporous silica thin film with pristine nanoporous thin film. We found little difference in surface morphology and microstructure between the two nanoporous thin films after reactive-ion etch. But the etch rate was significantly affected by the amount of carbon present in the silica matrix. This can be explained in terms of the dependence of the etch rate on the fluorine/carbon (F/C) ratio. The etch rate of the nanoporous silica thin film increases with the F/C ratio, plasma power and bias. For the post-etch pore formation process, the etch rate of the organic surfactant templated silica thin film was found to be comparable to that of a dense silica thin film.

摘要 i
Abstrate iii
致謝 v
目錄 vi
表目錄 ix
圖目錄 x
一、　　　　　 緒論 1
1.1　　 超大型積體電路技術現況及未來發展趨勢 1
1.2　　 研究動機及目的 5
二、　　　　　 文獻回顧 8
2.1　　 低介電常數薄膜材料 8
2.1.1　 基本特性與要求 9
2.1.2　 各種低介電材料介紹 10
2.2　　 奈米孔洞二氧化矽薄膜製備 21
2.2.1　 溶膠-凝膠（Sol-Gel）原理 21
2.2.2　 有機模板分子之自組裝 22
2.3 電漿蝕刻製程 25
2.3.1 電漿技術簡介 25
2.3.2　 蝕刻製程簡介 26
2.3.3 傳統二氧化矽介電材料蝕刻 28
2.3.4 多孔性二氧化矽薄膜蝕刻 30
2.3.5 光阻剝除 31
三、　　　　　 實驗 33
3.1　　 試片製備 33
3.1.1　 矽晶片清洗 33
3.1.2　 奈米孔洞二氧化矽薄膜前驅物配製 34
3.1.3　 奈米孔洞二氧化矽薄膜試片的製備 35
3.1.4　 HMDS疏水化改質處理 37
3.1.5　 利用反應性離子蝕刻系統(RIE)作薄膜的蝕刻 37
3.1.6　 利用Fusion ozone光阻去除系統進行薄膜上光阻的移除 38
3.2　　 利用微影-蝕刻製程製備高深寬比之溝渠 40
3.3 儀器分析原理 43
3.3.1　 傅立葉轉換紅外線光譜儀 43
3.3.2　 膜厚與折射率量測儀 (n&k analyzer) 44
3.3.3　 原子力顯微鏡(AFM) 44
3.3.4　 場發射掃描式電子顯微鏡(SEM) 46
3.3.5 X光繞射儀 (XRD) 47
3.3.6 奈米壓痕儀 (Nanoindentor) 48
四、　　　　　 結果與討論 51
4.1　　 不同的煅燒方式對製備奈米孔洞二氧化矽薄膜之影響 51
4.1.1　 以爐管加熱煅燒方式製備奈米孔洞二氧化矽薄膜 51
4.1.2　 以臭氧電漿氧化煅燒方式製備奈米孔洞二氧化矽薄膜 59
4.1.3　 結論 65
4.2　　 光阻移除對奈米孔洞二氧化矽薄膜性質之影響 66
4.2.1 利用臭氧電漿氧化法移除奈米孔洞二氧化矽薄膜上之光阻
對其薄膜性質之影響 66
4.2.2 光阻移除對三甲基矽化改質後之奈米孔洞二氧化矽薄膜
的性質影響 71
4.2.3 利用臭氧電漿氧化法同時移除模板分子及光阻來製備奈米
孔洞二氧化矽薄膜 76
4.2.4 結論 79
4.3 反應性離子蝕刻製程(RIE)對薄膜性質之影響 82
4.3.1 奈米孔洞二氧化矽薄膜於乾式蝕刻後之薄膜性質研究 82
4.3.2 三甲基矽化奈米孔洞二氧化矽薄膜於蝕刻後之薄膜性質研
究 87
4.3.3 有機模板分子於蝕刻後移除對二氧化矽薄膜的影響 90
4.3.4 結論 95
4.4 高密度電漿反應性離子蝕刻(HDP-RIE)製程之探討 97
4.4.1 探討不同的蝕刻參數對蝕刻性質之影響 97
4.4.1.1 感應耦合式電漿功率(ICP power)對蝕刻的影響 97
4.4.1.2 偏壓功率(Bias power)對蝕刻的影響 99
4.4.1.3 系統壓力對蝕刻的影響 99
4.4.1.4 蝕刻氣體配比(CHF3/Ar)對蝕刻的影響 101
4.4.1.5 蝕刻氣體配比(CF4/CHF3)對蝕刻的影響 102
4.4.2 製備厚膜以蝕刻出高深寬比之溝槽 106
五、　　　　　 結論 110
參考文獻 113

1. S. Bothra, B. Rogers, M. Kellam, IEEE Transactions on Electr. Dev., 40, 591 (1993).
2. T. Homma, Mater. Sci. Eng., 23, 243 (1998).
3. D. Edelstein et al., Tech. Dig. 376 (1997).
4. Havemenn, R. H., Low-Dielectric Constant Material IV, MRS Symp. Proc., 511, 3-14 (1998).
5. International Technology Roadmap for Semiconductors (ITRS), 2004 edition (http://public.itrs.net/).
6. P. Atkins and J. de Paula, Atkins’ Physical Chemistry, 7th ed. (Oxford University Press, New York, 2002).
7. S. O. Kasap, Principles of Electrical Engineering Materials and Devices (McGraw-Hill, New York, 1997), Chap. 7.
8. K. J. Miller, H. B. Hollinger, J. Grebowicz, and B. Wunderlich, Macromolecules, 23, 3855 (1990).
9. 陳耀騰，低介電材料簡介，塑膠資訊，專題報導，1-9頁，民國88年。
10. Tetsuo Matsuda, M. J. Shapiro, DUMIC Conference, p. 22 (1995).
11. Takashi Fukada, Takashi Akahori, International Conference on solid State Devices and Materials, p. 158 (1993).
12. Y. J. Mei, T. C. Chang, S. J. Chang, Thin Solid Films 308-309, 501 (1997).
13. K. Maex, M. R. Baklanov, J. Appl. Phys., 93, 8793 (2003).
14. W. C. Liu, C. C. Yang, Non-Cryst. Solids, 311, 233 (2002).
15. N. P. Hacker, J. S. Drage, VMIC Conference, p. 138 (1995).
16. Joanne Y. Chee, James S. Drage, VMIC Conference, p. 128 (1995).
17. Mckerrow, A. and Ho, P., In Low Dielectric Constant Materials and Interconnects Workshop Proc., 199, (1996).
18. R. N. Vrtis, K. A. Heap, W. F. Burgoyne, L. M. Robeson, VLSI Multilevel Interconnection Conference, p. 620 (1997).
19. S. C. Sun and Y. C. Chuang, VLSI Multilevel Interconnection Conference, p. 113 (1996).
20. 顧子琨，電子月刊，第五期第六卷，117-133頁，民國88年。
21. A trademark of Dow Chemical (http://www.dow.com).
22. P. H. Townsend, S. J. Martin, J. Godschal, D. R. Romer, D. W. Jr. Smith, D. Castillo, R. DeVries, G. Buske, N. Rondan, S. Froelicher, J. Marshall, E. O. Shaffer, and J. H. Im, Mater. Res. Soc. Symp. Proc., 476, 9 (1997).
23. M. E. Mills, P. Townsend, D. Castillo, S. Martin, and A.Achen, Microelectron. Eng., 33, 327 (1997).
24. H. Y, T. Hayashi, Appl. Phys. Lett., 72, 21 (1998).
25. D. Chao, P. Yang, N. Melosh, J. Feng, F. Chmelka, G. D. Stucky, Adv. Mater., 10, 1380 (1998).
26. M. Antonietti , B. Berton , C. Goltner , H. P. Hentze, Adv. Mater, (1997).
27. 陳麗梅，多孔低介電常數材料，電子月刊，第七期第四卷，130-137頁。
28. S. S. Prakash, C. J. Brinker, A. J. Hurd, J. Non-Cryst. Solids, 190, 264 (1995).
29. C. M. Jin, J. D. Luttmer, D. M. Smith, T.A. Ramos, MRS Bull, 22(10), 39 (1997).
30. D. M. Smith, J. Anderson, C. C. Cho, G. P.Johnston, S. P. Jeng, Mater. Res. Soc. Symp. Proc., 381, 261 (1995).
31. H. S. Yang, S. Y. Choi, S. H. Hyun, H. H. Park, J. K. Hong, J. Non-Cryst. Solids, 221, 151 (1997).
32. S. Acosta, A. Ayral, C. Guizard, C. Lecornec, G. Passemard, and M. Moussavi, Mater. Res. Soc. Symp. Proc., 612, D5.26.1 (2000).
33. S. Acosta, A. Ayral, C. Guizard, C. Lecornec, G. Passemard, and M. Moussavi, Mater. Res. Soc. Symp. Proc., 612, D5.26.1 (2000).
34. S. V. Nitta, V. Pisupatti, A. Jain, P. C. Wayner, Jr., W. N. Gill, and J. L. Plawsky, J. Vac. Sci. Technol. B, 17, 205 (1999).
35. T. Ramos, K. Roderick, A. Maskara, and D. M. Smith, Mater. Res. Soc. Symp. Proc., 443, 47 (1997).
36. A. M. Buckley and M. Greenblatt, J. Non-Cryst. Solids, 143, 1 (1992).
37. D. Zhao, P. Yang, N. Melosh, J. Feng, B. F. Chmelka, G. D. Stucky, Adv. Mater., 10, 1380 (1998).
38. Y. Lu, R. Ganguli, C. A. Drewien, M. T. Anderson, C. J. Brinker, W. Gong, Y. Guo, H. Soyez, B. Dunn, M. H. Huang, J. I. Zink, Nature, 389, 364 (1997).
39. C. J. Brinker, Y. Lu, H. Fan, and C.S. Sriram, Abstracts of the 1999 MRS Spring Meeting, April 5-9, p. 237.
40. S. Baskaran, J. Liu, K. Domansky, X. Li, N. Kohler, G. Fryxell, S. Thevuthasen and R.E. Williford, ibid, p.237.
41. C. J. Brinker, Y. Lu, A. Sellinger, and H. Fan, Adv. Mater., 11, 579 (1999).
42. C. J. Brinker and G. W. Scherer, Sol-gel Science (Academic Press, San Diego, 1990).
43. 羅正忠，張鼎張譯，半導體製程技術導論，歐亞圖書有限公司 (2002).
44. 施敏，半導體元件物理與製作技術，國立交通大學出版社 (2002).
45. 陳力俊，微電子材料與製程，中國材料科學學會 (2000).
46. T. E. F. M. Standaert, M. Schaepkens, N. R. Rueger, P. G. M. Sebel, G. S. Oehrlein, and J. M. Cook, J. Vac. Sci. Technol. A, 16, 239 (1998).
47. T. E. F. M. Standaert, P. J. Matsuo, S. D. Allen, G. S. Oehrlein, and T. J. Dalton, J. Vac. Sci. Technol. A, 17, 741 (1999).
48. T. E. F. M. Standaert, E. A. Joseph, G. S. Oehrlein, A. Jain, W. N. Gill, P. C. Wayner, Jr., and J. L. Plawsky, J. Vac. Sci. Technol. A, 18, 2742 (2000).
49. T. E. F. M. Standaert, C. Hedlund, E. A. Joseph, G. S. Oehrlein, and T. J. Dalton, J. Vac. Sci. Technol. A, 22, 53 (2004).
50. H.-H. PARK, M.-H. JO, H.-R. KIM, S.-H. HYUN, J. Mater. Sci. Lett., 17, 2083 (1998).
51. 汪建民，材料分析，中國材料科學學會 (1998).
52. 趙立德，奈米孔洞低介電常數材料在半導體製程整合上之研究，國立清華大學，碩士論文，民國90年。
53. Bharat Bhushan “Handbook of micro/nano tribology”2nd(2000).
54. E. E. Simonyi, K. W. Lee, R. F. Cook, E. G. Liniger, and J. Speidell , Mat. Res. Soc. Symp. Proc., 511, 157 (1998).
55. W. C. Oliver et. al, J. Mater. Res., 7 (6), (1992).
56. L. W. Hrubesh and J. F. Poco, Mater. Res. Soc. Symp. Proc., 371, 195 (1995).
57. Kee-Won, Changsup Ryu, Robert Sinclair, Appl. Phys. Lett., 75(7), 935 (1999).
58. R. J. Glexiner, W. D. Nix, J. Appl. Phys., 86(4), 1932 (1999).
59. C. C. Cho, D. M. Smith, J. Anderson, Mater. Chem. Phys., 42, 91 (1995).
60. E. O. Shaffer et. al, Mater. Res. Soc. Symp. Proc., 612, (2000).
61. 伍秀菁編輯，真空技術與應用，國科會精儀中心 (2001).
62. Henry Gerung, C. J. Brinker, Steven R. J. Brueck, J. Vac. Sci. Technol. A, 23(2), 347 (2000).