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研究生:王鍾儒
研究生(外文):Chung-Ju Wang
論文名稱:覆晶球柵陣列封裝之熱變形與熱應力分佈
論文名稱(外文):Thermal Deformations and Stress Distributions of Flip-Chip BGA Package under Thermal Environment
指導教授:趙魯平趙魯平引用關係
指導教授(外文):Lu-Ping Chao
學位類別:碩士
校院名稱:逢甲大學
系所名稱:機械工程學所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:112
中文關鍵詞:Twyman-Green干涉術覆晶相移術有限元素分析
外文關鍵詞:Twyman-Green InterferometryFlip ChipPhase-Shifting TechnologyFinite Element Analysis
相關次數:
  • 被引用被引用:1
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  • 下載下載:107
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隨著市場需求以及科技產業的進步,消費型電子產品及可攜式產品發展以輕薄短小及多功能等要素為目標,因此能提供優良電性效能、高接腳數以及縮小封裝尺寸之覆晶封裝技術便迅速普及,但在尺寸縮小的情形下,溫度可能造成之破壞更需要重視。由於覆晶球柵陣列封裝各層材料間的熱膨脹係數差異,會因受溫度升高時會造成熱應力產生,可能使構裝體本身產生破壞,造成電子元件之功能失效,因此能提供加熱環境下之有效全域式光學量測方法以及有限元素分析顯得更為重要。
本論文利用Twyman-Green干涉術為基礎,加入相位移技術作量測,其中相位移技術能提升干涉儀之解析度,減少人工判讀條紋之誤差。兩者搭配用以量測覆晶構裝試片在加熱環境下之變形行為,並透過ANSYS有限元素分析軟體提供三維模型之分析,其結果並與二維Suhir修正理論(由Tsai修正)解析解作比較。透過實驗之熱變形結果以驗證有限元素分析與理論解之正確性與適用性,以及將有限元素分析之熱應力與理論值比較,確認覆晶球柵陣列封裝之熱變形與熱應力分佈須以三維模型之有限元素分析方能完整表達,並可提供作為日後相關覆晶封裝結構設計分析時之重要方法。
Following the market demands and progress of science and technology, the development of consuming and portable electronics tend to become small, light, and multi-functional for recent years. For these requirements, flip chip technology has become popular rapidly owing to their high electronic performance, high I/O density, and smaller package size capabilities. However we should take thermal effects seriously because of packages may be damaged when package size became smaller. Therefore, it is significant that the measurement and estimation of thermal deformation behavior of chips by reliable whole-field optical method and finite element analysis.
In this thesis, we combined Twyman-Green interferometry with phase-shifting technique for the experimental measurement. Using the phase-shifting technique will improve resolution and practicability of interferometry, and reduce inaccuracy caused by counting fringe orders directly when applying Twyman-Green interferometry only. We measure thermal deformations of flip chip BGA package under thermal environment. Meantime we use finite element analysis software ANSYS for 3D model thermal stress analysis, then compared with the modified Suhir theoretical solution. After verifying validity between experimental results, finite element solution, and modified Suhir theoretical solution, we demonstrate that the thermal deformations, die stress, and shear stress distributions of flip chip BGA package can almost expressed by finite element analysis, thus they can provide a reliable methodology for design and analysis in the thermal effects of different types of flip chips.
中文摘要………………………………………………………i
英文摘要………………………………………………………ii
誌謝……………………………………………………………iii
目錄……………………………………………………………iv
圖目錄…………………………………………………………vii
表目錄…………………………………………………………xii
符號說明………………………………………………………xiii

第一章 緒論……………………………………………………1
1.1 研究背景與動機…………………………………………1
1.2 文獻回顧…………………………………………………6
1.2.1光學干涉術………………………………………………6
1.2.2數值模擬…………………………………………………6
1.2.3理論分析…………………………………………………7
1.3 研究方法…………………………………………………8
1.4 本文內容…………………………………………………9

第二章 理論基礎………………………………………………10
2.1 Suhir修正理論……………………………………………11
2.1.1 Suhir修正理論公式推導………………………………15
2.2有限元素數值模擬…………………………………………22
2.2.1 有限元素模型建立………………………………………23

第三章 光學量測方法………………………………………27
3.1 前言………………………………………………………27
3.2 干涉原理…………………………………………………28
3.2.1 干涉方程式推導………………………………………30
3.3 Twyman-Green干涉術……………………………………32
3.4 相移術……………………………………………………35
3.4.1 五一相移術……………………………………………37
3.5 光學干涉儀實驗設備……………………………………40

第四章 實驗結果與討論……………………………………45
4.1 前言………………………………………………………45
4.2 覆晶構裝試片……………………………………………46
4.3 光學量測結果……………………………………………48
4.4 數值模擬結果……………………………………………61
4.5 實驗與模擬數據比較……………………………………68

第五章 結論與未來展望……………………………………90
5.1 結論………………………………………………………90
5.2 未來展望與需改進之工作………………………………92

參考文獻………………………………………………………94
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