臺灣博碩士論文加值系統

整體非同步局部同步（GALS）設計對於實現非同步系統是個有效率的方式。但是一般非同步封裝電路所包的局部同步區塊工作在最壞情況的表現。為了達到平均情況的特性以及容易實現非同步系統，本論文提出一個多用途封裝電路內含控制電路與”可停止之時脈產生器（PCC）”以及”完成電路”合作。這些電路所組成的非同步封裝電路可用於同步電路和組合電路。此控制電路內含寫埠、讀埠和完成訊號處理電路。我們用兩種不同的方法設計：一種全為標準元件組成，使用者可用此版本在前段數位流程實現並驗證非同步系統；另一種則是用C元件（C-elements）實現，為了使非同步系統能有更好的效能如小面積和低耗能。再者，為了使得非同步系統中的資料正確地傳輸，三種非同步封裝電路的連接方式被介紹，分別為一對一、一對多及多對一。使用者能夠使用提出的非同步封裝電路建構出非同步系統，例如整體非同步局部同步（GALS）系統或是非同步管線（Pipeline）。最後我們分析此非同步封裝電路在兩級之間傳輸資料時所消耗的時間，並給使用者建議以能適當的使用此封裝電路。

Globally asynchronous locally synchronous (GALS) design is an efficient way to implement asynchronous systems. However, the locally synchronous (LS) modules with asynchronous wrappers make worst case performance. In order to achieve average case performance and facilitate asynchronous circuits design, this thesis proposes a general purpose wrapper that includes control circuits to cooperate with pausible clock controllers (PCC) and done circuits. The asynchronous wrappers using these circuits can wrap around not only synchronous blocks (with clock) but also combinational modules. The control circuits contain the write-port, read-port, and done-handling circuit. There are two implementations: one using standard cell library and the other using c-elements. The system using the former design can be implemented and verified conveniently using existing frond-end synchronous design flow. The latter is implemented for better performance, higher speed, smaller area and lower power consumption. Moreover, the proper ways of using the asynchronous wrappers for robust data communication in asynchronous systems are introduced. There are one-to-one, one-to-many and many-to-one communications. Users can use the wrappers to construct asynchronous systems such as GALS systems and asynchronous pipelines. Finally, the timing overhead of the asynchronous wrappers between local modules is analyzed. Guidelines for proper usage are also given.

摘要 i
Abstract ii
誌謝 iii
Contents iv
List of Figures vii
List of Tables x
Chapter 1 Introductions 1
1.1 Background 1
1.2 Motivation 2
1.3 Organization 3
Chapter 2 Basics of Asynchronous Design 4
2.1 Properties of Asynchronous Design 5
2.2 Typical Asynchronous Designs 6
2.3 Popular Handshake Protocols 8
2.3.1 Bundled-data 8
2.3.2 Dual-rail 10
2.4 C-elements 12
2.4.1 Implementations of C-elements 12
2.4.2 The C-element with Standard cells 16
2.5 Asynchronous Pipelines and Done circuits 19
2.6 Starvation and Blocking 21
2.7 Overview of GALS Design 21
2.8 Related Works of an Asynchronous Wrapper 24
Chapter 3 Proposed Asynchronous Wrappers 28
3.1 Structures of the Asynchronous Wrappers 29
3.1.1 The Asynchronous Wrapper for Combinational Module 29
3.1.2 The Asynchronous Wrapper for Synchronous Module 32
3.1.3 Latches or Flip-Flops for Registers 34
3.2 Implementation with Standard cells 35
3.2.1 Write-port and Read-port with Standard cells 35
3.2.2 Done-Handling Circuit with Standard cells 39
3.2.3 Pausible Clock Controller (PCC) with Standard cells 41
3.3 Implementation with C-elements 43
3.3.1 Write-port and Read port with C-elements 43
3.3.2 Done-Handling Circuit with C-elements 45
3.3.3 Pausible Clock Controller (PCC) with C-elements 46
3.4 Simulation Results of the Asynchronous Wrappers 47
3.5 Timing Constraints for Latches or Flip-Flops 53
Chapter 4 Communications with the Asynchronous Wrappers 57
4.1 One-to-one Communication 58
4.1.1 Structure of One-to-one Communication 58
4.1.2 One-to-one connection of the Asynchronous Wrappers 59
4.2 One-to-many and Many-to-one Communications 64
4.2.1 Structures of One-to-many and Many-to-one Communications 64
4.2.2 One-to-many and Many-to-one connections of the Asynchronous Wrappers 66
4.3 Timing Overhead of the Asynchronous Wrappers 67
4.4 Timing Overhead of Data Communication 68
4.5 Application 71
Chapter 5 Conclusions and Future Works 73
5.1 Conclusions 73
5.2 Future Works 74
References 75
Appendix 78

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