臺灣博碩士論文加值系統

　　為了增加低溫多晶矽薄膜電晶體的驅動電流，閘極介電層的微小化是有效的提升方法之一，因此高介電係數材料被提出，來取代傳統的二氧化矽，來改善電性。
　　在本論文中，我們提出高性能氮氧化矽和氧化釓高介電係數閘極介電層的低溫多晶矽薄膜電晶體。然而，高介電係數閘極介電層的多晶矽薄膜電晶體，有閘極感應汲極漏電流的問題，我們利用氟離子佈植方法來鈍化陷阱狀態密度，進而改善電性。並且探討氟離子佈植效應對氮氧化矽和氧化釓閘極介電層低溫多晶矽薄膜電晶體之特性。氟離子佈植改善了低溫多晶矽薄膜電晶體的電性，包含臨界電壓、次臨界擺幅、導通電流和截止電流比率、晶粒邊界狀態密度和表面狀態密度。
　　最後，我們也探討氟離子佈植效應對氮氧化矽和氧化釓閘極介電層p型通道低溫多晶矽薄膜電晶體的負偏壓溫度不穩定效應。因為矽和氟的鍵結能量大於矽和氫的鍵結能量，所以矽和氟鍵結較能穩定對抗負偏壓溫度不穩定的應力。因此，氟離子佈植在低溫多晶矽薄膜電晶體不但能有效改善電性並且增加可靠度。

For enhance of the driving current of LTPS TFTs, scaling down of the gate dielectric thickness is an effective method. Recently, several high-k materials have been investigated instead of conventional SiO2 gate dielectric to improve electrical characteristics.
In this thesis, we proposed the high performance low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) integrated high-K SiON and Gd2O3 gate dielectric. However, poly-Si TFTs with high-k gate dielectric would suffer from a more undesirable gate-induced drain leakage (GIDL) issue. We utilized F-ion implantation to passsivate trap state density to improve electrical characteristics. And study characterization of F-ion implant effects on LTPS TFTs with SiON and Gd2O3 gate dielectrics. The electrical characteristics of LTPS TFTs with SiON and Gd2O3 gate dielectrics were improved　by F-ion implantation, including threshold voltage, subtheshold swing, Ion/Ioff ratio, grain-boundary trap density, and interface trap state density.
Finally, we also study the negative bias temperature instability (NBTI) reliability for SiON and Gd2O3 gate dielectrics p-channel LTPS TFTs with fluorine implantation. Because the Si-F binding energy was lager than Si-H binding energy resulting in Si-F bonds have stable against the NBTI stress. Therefore, fluorine implanted LTPS TFTs can effectively improve the electrical characteristic and enhance the thermal reliability.

Contents

Acknowledgment i
Chinese Abstract ii
English Abstract iii
Contents iv
Content of Figures vi
List of Tables ix
Chapter 1 Introduction.....................................1
1.1 Background.....................................1
1.2 Motivation.....................................3
1.3 Thesis Organization............................3
Reference..........................................6
Chapter 2 Characterization of Fluorine-Ion Implant effect on
p-channel LTPS TFTs with SiON Gate Dielectric....8
2.1 Introduction...................................8
2.2 Polyoxide capacitors experiments...............9
2.2.1 Process for polyoxide capacitors..........9
2.2.2 Results and Discussion for polyoxide
capacitor................................11
2.3 F-ion implantation LTPS TFTs with SiON
experiments...................................11
2.3.1 Process for F-ion implantation LTPS TFTs
with SiON gate dielectric................11
2.3.2 Results and Disscussion for F-ion
implantation LTPS TFTs with SiON gate
dielectric...............................12
2.4 Summary.......................................15
Reference.........................................30
Chapter 3 Characterization of Fluorine-Ion Implant effects
on p-channel LTPS TFTs with Gd2O3 Gate
Dielectric......................................32
3.1 Introduction..................................32
3.2 Experiments...................................33
3.3 Results and discussion........................34
3.4 Summary.......................................36
Reference.........................................44
Chapter 4 Characteristics of Negative Bias Temperature
Instability for p-channel LTPS TFTs with SiON and
Gd2O3 by Fluorine Ion Implantation..............46
4.1 Introduction..................................46
4.2 Experiments...................................47
4.3 Results and Discussion........................48
4.4 Summary.......................................50
Reference.........................................59
Chapter 5 Conclusions and Future Works....................61
5.1 Conclusion....................................61
5.2 Future works..................................62

Content of Figures

Fig. 1-1 The transition of lifetime limitation mechanism as
a function of gate oxide thickness................5
Fig. 2-1 The schematic cross-sectional view of
SiO2/polysilicon interface (a)Only hydrogenated
TFT (b)Fluorinated and hydrogenated TFT.........16
Fig. 2-2 Schematic of process for fabrication of polyoxide
capacitors.......................................18
Fig. 2-3 The high frequency C-V characteristics of
aluminum /polyoxide/ n+-polysilicon for control
NH3=0............................................19
Fig. 2-4 The high frequency C-V characteristics of
aluminum /polyoxide / n+-polysilicon for control
NH3=20sccm.......................................19
Fig. 2-5 The high frequency C-V characteristics of
aluminum /polyoxide / n+-polysilicon for control
NH3=50sccm.......................................20
Fig. 2-6 The high frequency C-V characteristics of
aluminum /polyoxide / n+-polysilicon for control
NH3=80sccm.......................................20
Fig. 2-7 The J-E characteristics of the four condition on
n+-polysilicon films for the top gate applied with
a negative bias..................................21
Fig. 2-8 The J-E characteristics of the four condition on
n+-polysilicon films for the top gate applied with
a positive bias..................................21
Fig. 2-9 The Weibull distribution breakdown field plots for
four conditions n+-polysilicon films for the top
gate applied with a negative gate bias...........22
Fig. 2-10 The Weibull distribution breakdown field plots
for four conditions n+-polysilicon films for the
top gate applied with a positive gate bias......22
Fig. 2-11 Schematic of process for fabrication of LTPS TFTs
with fluorine-implanted.........................25
Fig. 2-13 Output characteristics of the SiON LTPS TFTs with
and without fluorine ion implantation...........26
Fig. 2-14 Transfer characteristics of the SiON LTPS TFTs
with and without fluorine ion implantation......27
Fig. 2-15 The grain boundary trap states extraction of the
SiON LTPS TFTs with and without fluorine ion
implantation....................................27
Fig. 2-16 Hysteresis phenomenon of p+-poly gate/ SiON/ p+-
polysilicon capacitors (a) without and (b) with F- ion implantation in poly-Si substrate...........28
Fig. 3-1 Schematic of process for fabrication of LTPS TFTs
with fluorine-implanted..........................39
Fig. 3-2 The C-V characteristics of the Gd2O3 LTPS TFTs
with and without fluorine ion implantation.......40
Fig. 3-3 Output characteristics of the Gd2O3 LTPS TFTs with
and without fluorine ion implantation............40
Fig. 3-4 Transfer characteristics of the Gd2O3 LTPS TFTs
with and without fluorine ion implantation.......41
Fig. 3-5 The grain-boundary trap-states extraction of the
Gd2O3 LTPS TFTs with and without fluorine ion
implantation.....................................41
Fig. 3-6 Hysteresis phenomenon of p+-poly gate/ Gd2O3/ p+-
polysilicon capacitors (a) without and (b) with F-
ion implantation in poly-Si substrate............42
Fig. 4-1 Schematic cross-sectional diagram of the SiON and
Gd2O3 LTPS TFTs and NBTI stress setup............52
Fig. 4-2 NBTI stress for (a) Vth shift (b) the drive
current degradation of the SiON LTPS TFTs and
without F-ion implantation in poly-Si substrate…53
Fig. 4-3 NBTI stress for (a) Vth shift (b) the drive
current degradation of the SiON LTPS TFTs with F-
ion implantation in poly-Si substrate............54
Fig. 4-4 NBTI stress for (a) Vth shift (b) the drive
current degradation of the Gd2O3 LTPS TFTs and
without F-ion implantation in poly-Si substrate..55
Fig. 4-5 NBTI stress for (a) Vth shift (b) the drive
current degradation of the Gd2O3 LTPS TFTs with F-
ion implantation in poly-Si substrate............56
Fig. 4-6 Schematic energy band diagram of (a) SiON LTPS
TFTs (b) Gd2O3 LTPS TFTs under NBTI stress.......57

List of Tables

Table 2-1 Device parameters of SiON LTPS TFTs for with and
without fluorine implantation at VDS= -0.1V.....29
Table 3-1 Device parameters of Gd2O3 LTPS TFTs for with and
without fluorine implantation at VDS= -0.1V.....43
Table 4-1 Device parameters of SiON LTPS TFTs by NBTI
stress for different stress bias and different
temperature.....................................58
Table 4-2 Device parameters of Gd2O3 LTPS TFTs by NBTI
stress for different stress bias and different
temperature.....................................58
Table 5-1 Device parameters of SiON and Gd2O3 LTPS TFTs by
NBTI stress for different stress bias and
different temperatur............................63

Chapter 1

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chapter 2

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[3] Morimoto, Y., Jinno, Y., Hirai, K., Ogata, H., Yamada, T., Yoneda, K., “Influence of the grain boundaries and intragrain defects on the performance of poly-Si thin film transistors,” Journal of the Electrochemical Society, vol. 144, pp. 2495-2501. July 1997.
[4] Wu, I-Wei, Jackson, Warren B., Huang, Tiao-Yuan, Lewis, Alan G., Chiang, Anne, “Mechanism of device degradation in n- and p-channel polysilicon TFT's by electrical stressing,” Electron device letters, vol 11, pp. 167-170. April 1990.
[5] Chern, Horng Nan, Lee, Chung Len, Lei, Tan Fu, “Effects of fluorine passivation on polysilicon thin-film transistors,” IEEE Transactions on Electron Devices, 41, pp. 698-702. May 1994.
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Chapter 3

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[4] Morimoto, Y., Jinno, Y., Hirai, K., Ogata, H., Yamada, T., Yoneda, K., “Influence of the grain boundaries and intragrain defects on the performance of poly-Si thin film transistors,” Journal of the Electrochemical Society, vol. 144, pp. 2495-2501. July 1997.
[5] Wu, I-Wei, Jackson, Warren B., Huang, Tiao-Yuan, Lewis, Alan G., Chiang, Anne, “Mechanism of device degradation in n- and p-channel polysilicon TFT's by electrical stressing,” Electron device letters, vol 11, pp. 167-170. April 1990.
[6] Chern, Horng Nan, Lee, Chung Len, Lei, Tan Fu, “Effects of fluorine passivation on polysilicon thin-film transistors,” IEEE Transactions on Electron Devices, 41, pp. 698-702. May 1994.
[7] Yang, C.K., Lei, T.F., Lee, C.L., “Characteristics of top-gate polysilicon thin-film transistors fabricated on fluorine-implanted and crystallized amorphous silicon films,” Journal of the Electrochemical Society, vol. 143, pp. 3302-3307. October 1996.
[8] J. Levinson et al., “Conductivity behavior in polycrystalline semiconductor thin film transistors” Journal of applied physics, vol. 53, pp. 1193-1202, February 1982.
[9] R. E. Proano et al., “Development and Electrical Properties of Undoped Polycrystalline Silicon Thin-Film Transistors” IEEE Transactions On Electron Devices, vol. 36, pp.1915-1922, September 1989.
[10] Chih-Yang Chen et al., “Negative Bias Temperature Instability in Low-Temperature Polycrystaline Silicon Thin-Film Transistors” IEEE Transactions On Electron Devices, vol. 53, No. 12, pp. 2993-3000, December 2006.

Chapter 4

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[10] Maegawa, S., Ipposhi, T., Maeda, S., Nishimura, H., Ichiki, T., Ashida, M., Tanina, O., Inoue, Y., Nishimura, T., Tsubouchi, N., “Performance and Reliability Improvements in Poly –Si TFT’s by Fluorine Implantation into Gate Poly-Si,” IEEE Trans. Electron Devices, vol. 42, pp. 1106–1112, June 1995.