臺灣博碩士論文加值系統

非揮發性記憶體(nonvolatile memory；NVM)在元件尺寸持續微縮下的目的為高密度記憶單元、低功率損耗、快速讀寫操作、以及良好的可靠度(reliability)。傳統浮動閘極(floating gate)記憶體在操作過程中如果穿隧氧化層產生漏電路徑會造成所有儲存電荷流失回到矽基板，所以在資料保存時間(retention)和操作耐久性(endurance)的考量下，很難去微縮穿隧氧化層的厚度。我們利用GeO2以及Ge3N4本身含有很多陷阱(trap)，可當作彼此分離的儲存點，改善小尺寸記憶體元件多次操作下的資料儲存能力。
在本論文中，我們用一個簡單的製程方法來形成鍺化物如：GeO2以及Ge3N4，探討其作為儲存材料的特性。在SONOS記憶體元件中以Si3N4作為電荷儲存層，GeO2的傳導帶(conduction band)比起Si3N4的傳導帶低約(~0.7 ev)理論上是可以有效地改善資料儲存能力；若以Ge3N4作為電荷儲存層材料，Ge3N4的傳導帶比起Si3N4的傳導帶低約(~0.7 ev)理論上是可以有效地改善資料儲存能力，而且Ge3N4的介電係數(~9.6)比起Si3N4(~7.4)來得高，可讓施加的閘極電壓更有效的落在穿隧氧化層，以提高元件操作效率。最後利用製作完成的電容元件，做以下幾項電性量測包含：電容量測、資料保存時間量測、寫入/抹除速度量測、操作耐久性量測等。藉由以上之量測，我們可以清楚地知道我們製作元件之特性，並得知影響元件特性之原因與元件結構之關鍵點。

圖目錄
第一章 序論 ………………………………………………………………………1
1.1 前言……………… ……………………………………1
1.2 記憶體元件發展 …………………………………… 1
1.3 研究動機…………………………………………… …2
第二章 非揮發性記憶體的基本概念 …………………………5
2.1 前言 …………………………………………………… ……5
2.2.1 磁滯曲線 …………………………………………………5
2.2.2 寫入/抹除機制 ……………………………………………8
2.2.3 可靠度分析 ………………………………………… ……10
第三章 GeO2作為電荷儲存層的記憶體特性………………… 16
3.1 GeO2和Ge的特性比較 …………………………………… …16
3.1.1元件結構及實驗步驟 ………………………………………16
3.1.2 材料分析 ………………………………………………17
3.1.3電容-電壓特性與磁滯量測 …………………………… …17
3.1.4閘極漏電流量測 ……………………………………………18
3.1.5寫入與抹除量測………………………………………… …19
3.1.6操作耐久性的量測 …………………………………………19
3.1.7資料保存能力的量測 ………………………………………20
3.2 O2退火溫度對GeO2電性的影響 …………………… ………29
3.2.1元件結構及實驗步驟 ………………………………………29
3.2.2電容-電壓特性與磁滯量測 …………………… …………29
3.2.3閘極漏電流量測 ……………………………………………30
3.2.4寫入與抹除量測 ……………………………………………30
3.2.5操作耐久性的量測 …………………………………………30
3.2.6資料保存能力的量測 ………………………………………31
第四章 Ge和Ge3N4作為電荷儲存層的特性比 ……… ………39
4.1元件結構及實驗步驟 …………………………………………39
4.2電容-電壓特性與磁滯量測……………………………………39
4.3平帶電壓受頻率影響之量測 …………………………………40
4.4閘極漏電流量測 ………………………………………………41
4.5寫入與抹除量測 ………………………………………………41
4.6操作耐久性的量測 ……………………………………………41
4.7資料保存能力的量測 …………………………………………42
第五章 總結與未來展望 ………………………………………49
參考文獻 …………………………………………… ……………51

[1.1] D. Kahng and S. M Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech, J., vol. 46, p. 1288, 1967.
[1.2] J. D. Blauwe, “Nanocrystal nonvolatile memory devices,” IEEE Transaction on Nanotechnology, vol. 1, p. 72, 2002.
[1.3] J. S, Witters, G. Groeseneken and H. E. Maes, “Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits,” IEEE Journal of Solid State Circuits, p. 1372, 1989.
[1.4] M. H. White, Y. Yang, A. Purwar, and M. L. Frech, “A low voltage SONOS nonvolatile semiconductor memory technology,” IEEE Nonvolatile Memory Technology Conference, p. 52, 1996.
[1.5] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS,” IEEE circuits & devices, vol.16, p. 22, 2000.
[1.6] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage,” IEDM Tech. Dig., p. 521, 1995.
[1.7] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory,” IEEE Electron Device Lett., vol. 18, p. 278, 1997.
[1.8] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystal formed by thermal oxidation of Si1-xGex,” IEDM Tech. Dig., p. 115, 1998.
[1.9] S. Choi, M. Cho, and H. Hwang, “Improved metal-oxide-nitride- oxide-silicon-type flash device with high-k dielectrics for blocking layer, ” J. Appl. Phys., vol. 94, pp. 5408-5410, 2003.
[1.10] S. Choi, M. Cho, C. B. Samantaray, S. Jeon, C. Kim, and H. Hwang, “Improved charge-trapping nonvolatile memory with Dy-doped HfO2 as charge-trapping layer and Al2O3 as blocking layer,” Jpn. J. Appl. Phys., vol. 43, pp. L882-L884, 2004.

[2.1] P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission in n-channel IGFETs,” IEEE Solid-State Circuits, vol. 14, p. 442, 1979.
[2.2] M. Lenzlinger, “Fowler-Nordheim tunneling in thermal grown SiO2,” Appl. Phys. Lett., vol. 40, pp. 278-283, 1969.
[2.3] Donald A. Neamen, “Semiconductor physics and device,” p. 43.
[2.4] Stanley. Wolf, “Silicon processing for the VLSI ERA,” Lattice Press., p. 435, 1995.
[2.5] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, Proceedings of The IEEE, vol. 85, p. 1248, 1997.
[2.6] D. Ielmini, A. Spinelli, A. Lacaita, and A. Modelli, “Statistical model of reliability and scaling projections for Flash memories,” IEDM Tech. Dig., pp. 3221–3224, 2001.
[2.7] D. Ielmini, A. S. Spinelli, A. L. Lacaita, L. Confalonieri, and A. Visconti, “New technique for fast characterization of SILC distribution in Flash arrays,” Proc. IRPS., pp. 73–80, 2001.
[2.8] D. Ielmini, A. S. Spinelli, A. L. Lacaita, R. Leone, and A. Visconti, “Localization of SILC in flash memories after program/erase cycling,” Proc. IRPS., pp. 1–6, 2002.

[3.1] H. Choi, M. Chang, M. Jo, “Improved memory characteristics of Ge nano-crystals using a LaAlO3 buffer layer,” Electrochemical and Solid-State Lett., vol. 11, pp. H154-H156, 2008.
[3.2] C. L. Yuan, and P. S. Lee, “Enhanced charge storage capability of Ge/GeO2 core/shell nanostructure,” Nanotechnology, vol. 19, p. 355206, 2008.
[3.3] S. Huang, S. Banerjee, R. T. Tung, and S. Oda, “Electron trapping, storing, and emission in nano-crystalline Si dots by capacitance–voltage and conductance–voltage measurements,” J. Appl. Phys., vol. 93, pp. 576-581, 2003.
[3.4] J. Y. Tseng, C. W. Cheng, S. Y. Wang, T. B. Wu, “ Memory characteristics of Pt nano-crystals self-assembled from reduction of an embedded PtOx ultrathin film in metal-oxide-semiconductor structures,” Appl. Phys. Lett., vol. 85, pp. 2595-2597, 2004.
[3.5] C. L. Heng, T. G. Finstad, “Electrical characteristics of a metal-insulator- semiconductor memory structure containing Ge nano-crystals,” Phys. E, vol. 26, pp. 386-390, 2005.
[3.6] C. C. Wang, Y. K. Chiou, C. H. Chang, J. Y. Tseng, L. J. Wu, C. Y. Chen and T. B. Wu, “Memory characteristics of Au nano-crystals embedded in metal-oxide- semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide,” J. Phys. D, vol. 40, pp. 1673-1677, 2007.
[3.7] J. C. Wang, S. H. Chiao, C. L. Lee, T. F. Lei, Y. M. Lin, M. F. Wang, S. C. Chen, C. H. Yu, and M. S. Liang, “A physical model for the hysteresis phenol- menon of the ultrathin ZrO2 film,” J. Appl. Phys., vol. 92, pp. 3936-3940, 2002.
[3.8] K. Prabhakaran, F. Maeda, Y. Watanabe, and T. Ogino, “Distinctly dfferent theramal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces ” Appl. Phys. Lett., vol. 76, pp. 2244-2246, 2000.
[3.9] Y. Kamata, “High-k/Ge MOSFETs for future nano-electronics,” Materialstoday, vol. 11, pp. 30-38, 2008.