臺灣博碩士論文加值系統

首先我們研發出一種新的製程技術包括:電子束寫入、化學微縮以及二氧化矽蝕刻用來製作低於60奈米的接觸孔洞。接著使用CHF3/CF4混合的氣體蝕刻二氧化矽以形成奈米尺度大小的接觸孔洞。在蝕刻過程中，化學微縮阻劑在電漿蝕刻時側壁會形成高分子聚合物使得奈米孔洞縮小。孔洞的周長面積比例反應出經過蝕刻後孔洞尺寸的縮小情形，尤其對於小尺寸的接觸孔洞。蝕刻時在側壁形成的高分子聚合物可有效的縮小奈米孔洞尺寸。
再者將碳六十和碳七十加入電子束阻劑，稱為電子束阻劑修飾法，藉由加入少量的碳六十和碳七十，即可得到高解析度、小線寬以及高抗蝕刻能力之阻劑。使用阻劑修飾法可定義出低於50奈米的接觸孔洞及線、亦可應用在定義自我對準金屬矽化物的複晶矽以得到較低奈米線的片電阻值。本方法亦可增加阻劑對二氧化矽及複晶矽的選擇蝕刻比。
接著，我們使用鎳金屬自我對準矽化物和氨電漿處理來製作50奈米閘極長度的奈米鰭型元件。我們發現元件特性使用深層鎳金屬自我對準矽化物製程與沒有使用鎳金矽化物製程比較可以得到有效的改善，包括：次臨界擺動、汲極引發位能障降低、提升元件電流導通關閉比，。深層鎳金屬自我對準矽化物元件可以有效的抑制浮接基體效應和寄生BJT效應。
再來，我們發展一個非常簡單製備二氧化鋯薄膜的方法，包含：在冰浴中製備ZrCl4前驅物、溶膠-凝膠法沉積、烘烤以及退火等步驟。我們可使用前驅物的濃度控制薄膜厚度。關於薄膜的電性方面，如：有大的崩潰電場、低的閘極漏電流密度顯示出經過了900度的快速熱退火後，具有絕佳的絕緣體特性。使用溶膠-凝膠法製備的二氧化鋯薄膜可應用在電容的絕緣材料上。
最後我們使用簡單的溶膠法以及900度的快速熱退火來製備三種SONOS型記憶體元件,其一為以二氧化鉿薄膜作為SONOS型記憶體元件的陷捕電荷層,其二為以氧化鉿奈米微晶粒作為SONOS型記憶體元件的陷捕電荷層,其三為以氧化鋯和氧化鉿奈米微晶粒共存作為SONOS型記憶體元件的陷捕電荷層。這是溶膠法第一次使用在奈米微晶粒的記憶體元件製備上。SONOS型記憶體元件以氧化鋯和氧化鉿奈米微晶粒共存作為陷捕電荷層有較大的臨限電壓漂移和較快的寫入、清除。此外這三種SONOS型記憶體元件電性方面都有不錯的特性表現，如: 長時間的資料持久性，以及好的寫入、清除操作造成的性能退化少特性。

Contents
Abstract (Chinese) …………………………………………………...……………. I
Abstract (English) …………………………………...……………….…………….III
Acknowledge …………………………...…………………………………………… .V
Contents ………………………………………………………...…………………..VI
Figure Captions & Table Lists .………………………..….………………….........IX

Chapter 1 Introduction ………..…………………………………………………….1
1.1 Background….....…………………………………………..…..……………...1
1.2 Motivation ……………….…………………………………………..…...…...4
1.3 Thesis Organization …………………….……………………………………..6

Chapter 2 Fabrication of Sub-60-nm Contact Holes in Silicon Dioxide Layers.....8
2.1 Introduction …………………………….………………………………....…..8
2.2 Experimental ….....………..…………………...……………………..………..9
2.3 Results and discussion …………………………………………………....…..10
2.3.1 Chemical shrinkage processes for the electron-beam resist……………10
2.3.2 Fabrication of 53-nm contact holes…………………………………….12
2.4 Summary………………………………………………….……………….…14

Chapter 3 Resist Nano-modification Technology for Enhancing the Lithography and Etching Performance for Nano Contact Hole and Line
………………………………………………………………………………………..30
3.1 Introduction…………………………………………………………………..30
3.2 Experimental…………………………………………………..……………..31
3.3 Results and Discussion……………………………………………………….34
3.3.1 Enhancement of lithographic performance……………………….……34
3.3.2 Enhancement of etching performance..…………………….………......37
3.3.3 Application of fullerene-incorporated resists for nano-silicide gate and the electrical properties….………………………………………...……......38
3.3.4 Application of fullerene-incorporated resists for patterning and filling the contact hole….………………………………………………………......39
3.4 Summary..……………………………...…………….....…………………...41

Chapter 4 The impact of deep Ni salicidation and NH3 plasma treatment on nano-SOI FinFETs…………………………………………………..………….…..67
4.1 Introduction…………………………………………………………………..67
4.2Experimental…………… ……………………………………..……………..68
4.3 Results and Discussion……………………………………………………….69
4.4 Summary……………………………………………….………………..…...70

Chapter 5 Physical Characterization and Electrical Properties of Sol-Gel-Derived Zirconia Films…………………………………………………....78
5.1 Introducion…………………………….……………………………………..78
5.2 Experimental ......……………………………………………….……………80
5.3 Results and Discussion …………………………………………..………….82
5.4 Summary ..…………………………………………………………………...87

Chapter 6 Novel Sol-Gel Derived SONOS-TypeMemory…….…….…………...112
6.1 Introducion…………………………….………………….……………..….112
6.2 Experimental ......………………………………………..……….…………113
6.3 Results and Discussion …………………………………………..……..…114
6.3.1 Physical Characteristics…………………………...…………………114
6.3.2 Electrical Characteristics…………………………………….………116
6.4 Summary ..…………………………………………………...………….....119

Chapter 7 Conclusions and Recommendations for Future Works…………….156
7.1 Conclusions…………..…………………….………………………………156
7.2 Recommendations for Future Works………………………………………158
Reference…………………………………………………………………………..159
Vita (in Chinese)…………………………………………………………………...167
Publication list…………………………………………………………………..…168

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