臺灣博碩士論文加值系統

SoC的驗証已經成了一個非常重要及充滿挑戰性的工作。在傳統的設計過程中，軟體及硬體通常是分開設計的，這種方式減少了市埸的競爭性，再加上SoC 晶片包含了很多元件，例如 : CPU、時間計數器、記憶體、及嵌入式軟體等，這使得晶片變得愈來愈大，而且也愈來愈複雜。另外，硬體通常是在RTL level中實作的，這樣模擬需要花很多的時間，因此我們必須用更高的層級來描述整個設計。所以這篇論文的主要目的是要探討SoC的整合及驗証，我們使用JPEG2000為例子，以SystemC為環境來探討許多驗証上的問題。
首先，我們實作了一個EBCOT IP，我們使用了很多方法來加快EBCOT的執行速度 ; 再來，我們用SystemC 建構了整個JPEG2000 壓縮系統，而且將EBCOT整合到這個系統中 ; 最後，我們用Cocentric 來模擬整個JPEG2000的縮壓過程。

Design verification at system level has been one of the most important and challenging jobs for system design. It is because that traditionally, hardware and software are often developed separately. The sequential process of hardware and software development increases time-to-market. In addition, a system-on-chip comprises of many components such as processors, timers, busses, memories and embedded software. Designs are getting bigger in size and larger in complexity. Furthermore, hardware often implement at the RTL level, the simulation of which take much time. These demand designers to describe designs at higher levels of abstraction. The purpose of this thesis is to investigate and practice system level integration and verification. We use JPEG2000, an image compression standard as a design vehicle to explore many system verification problems using SystemC.
The major contributions of this thesis are summarized as follows. First, we implement/verify the EBCOT hardware design. To speedup the design, we have use pixel skipping, column based operation and pipeline techniques. The second contribution of this thesis is to build the entire system of JPEG2000 using both systemC and RTL verilog. The system allows us to verify the correctness of software and hardware together, and we can use this system to do lossless compression. Finally, we have integrated and performed simulation on both the SystemC and Verilog together. The platform used for integration is a tool called Cocentric.

Abstract 4
Contents 5
List of Figures 6
List of Tables 7
Chapter1 Introduction 8
Chapter2 Background 12
2.1 JPEG2000 12
2.1.1 JPEG2000 Algorithms 15
2.2 SystemC 20
2.2.1 SystemC Design Methodology 21
2.2.2 SystemC modeling review 22
Chapter3 EBCOT Implementation and System Design 23
3.1 EBCOT Architecture 23
3.1.1 Memory interface 24
3.1.2 Context formation 25
3.1.3 arithmetic encoder 26
3.2 System Structure 28
3.2.1 the bus module 29
3.2.2 arbiter 30
3.2.3 memory 30
3.2.4 software 31
3.2.5 EBCOT 32
3.3 Co-Simulation 33
Chapter4 Experimental results 35
Chapter5 Conclusions 36
Bibliography 37

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