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研究生:洪國瑋
研究生(外文):Hung, Kuo-Wei
論文名稱:基於硬體計數器之微處理器靜態功耗估計
論文名稱(外文):Estimating Static Power Consumption of Microprocessors Using Performance Counters
指導教授:曹孝櫟曹孝櫟引用關係
口試委員:李皇辰賴槿峰
口試日期:2015-10-26
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊科學與工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:104
語文別:英文
論文頁數:49
中文關鍵詞:微處理器硬體計數器漏電流耗電模型
外文關鍵詞:MicroprocessorStatic PowerLeakage PowerPower ModelPerformance Counter
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如何在能源有限的嵌入式環境中取得效能與耗能平衡一直是重要的研究議 題,因此有不少人提出即時性電源管理的機制。而為了提供最佳電源管理效果, 能得知即時耗電資訊是必要的。即時評估耗電的方法大致可分為兩種,一種是透 過電源感測器,另一種是基於硬體計數器所建立的耗電模型。本論文屬於基於硬 體計數器的耗電模型。過去有許多研究專注於增進耗電模型準確率,但大多數的 情況下,動態耗電佔據大部分總體耗電,然而隨著互補式金屬氧化物半導體製程 技術演進,靜態耗電反而成了總體耗電的主角。微處理器劇烈的工作溫度變化, 大大影響了靜態耗電,而過去評估耗電的模型也顯得不再適用。
本論文分別對影響動態耗電以及靜態耗電的硬體計數器進行分析,以提高評 估耗電的準確率,並提出基於硬體計數器的耗電模型。
The tradeoff between power consumption and performance of microprocessor is a major consideration issue in embedded devices with limited energy resource. Therefore, several power management technologies are proposed to reduce power consumption at runtime. These technologies require the status of power consumption at runtime to manage strategy. The techniques can be divided into two major categories, which are meter-based and counter-based, respectively. In this thesis, we focus on the domain of counter-based evaluation, which is computing power consumption based on the information of performance counters at runtime. To improve the accuracy of counter-based evaluation, several power models are proposed in last decades. Moreover, most of the previous studies consider dynamic power as the major factors in the power models. However, the static power dominates the power consumption of microprocessor while complementary metal-oxide-semiconductor (CMOS) processes improving. Furthermore, the variation of static power at runtime is intensifying since the operating temperature of microprocessor is elevating. These phenomena can result in the traditional power models is not suitable for the microprocessor produced in advanced-technology.
In this thesis, we proposed a power model which considers and evaluates dynamic and static power simultaneously. This can increase the accuracy power model while it is applied to microprocessor with advanced technology. Also, we analyze the major performance counters which can be applied to evaluate static and dynamic power, respectively.
I. Introduction .................................................................................................. 1
II. Related work................................................................................................. 4
III. Approaches ................................................................................................... 6
IV. Simulation Platform for Microprocessors ............................................... 11
V. Experimental Setup ................................................................................... 27
VI. Experimental Results ................................................................................. 30
VII. Conclusion .................................................................................................. 46
Reference ....................................................................................................................47
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[2] Dev. K, Nowroz. A.N., Reda. S, “Power Mapping and Modeling of Multi-Core Processors,” IEEE Low Power Electronics and Design (ISLPED), 2013
[3] Kim, Yeong-Jun, et al. “Fast and accurate power estimation method based on a PMU counter.” Proceedings of the 8th International Conference on Ubiquitous Information Management and Communication. ACM, 2014.
[4] Kawaguchi, S. and T. Yachi (2014), “Adaptive power efficiency control by computer power consumption prediction using performance counters,” Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE-ASIA), 2014 International.
[5] M.S. Floyd et al., “Introducing the Adaptive Energy Management Features of the POWER7 Chip,” IEEE Micro, vol. 31, no. 2, pp. 60-75, Mar./Apr. 2011.
[6] R. Jotwani et al., “An x86-64 Core Implemented in 32nm SOICMOS,” Proc. IEEE Int’l Solid-State Circuits Conf. Digest of Technical Papers (ISSCC ’10), Feb. 2010.
[7] B. Stackhouse et al., “A 65nm 2-Billion-Transistor Quad-Core Itanium 1 Processor,” Proc. IEEE Int’l Solid-State Circuits Conf. Digest of Technical Papers (ISSCC ’08), 2008.
[8] K. K. Pusukuri et al., “A methodology for developing simple and robust power models using performance monitoring events,” in WIOSCA, 2009.
[9] K. Singh, M. Bhadauria, and S. McKee, “Real time power estimation and thread
scheduling via performance counters,” ACM SIGARCH Computer Architecture
News, vol. 37, no. 2, pp. 46–55, 2009.
[10] Bertran, R., Gonzalez, M., Martorell, X., Navarro, N., and Ayguade, E. “Decomposable and responsive power models for multicore processors using performance counters.” ICS ’10: Proceedings of the 24th ACM International Conference on Supercomputing, Tsukuba, Ibaraki, Japan, June, pp. 147–158. ACM
[11] Bircher, W. L. and John, L. K. “Complete system power estimation using processor performance events.” IEEE Transactions on Computers, 61. 2012.
[12] R. Bertran, M. Gonzalez, X. Martorell, N. Navarro, and E. Ayguade, “A
systematic methodology to generate decomposable and responsive power models for CMPs,” IEEE Transactions on Computers, vol. 62, no. 7, pp. 1289–1302, 2013.
[13] Jacobson, Hans, et al. "Abstraction and microarchitecture scaling in early-stage power modeling." High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on. IEEE, 2011.
[14] Binkert, Nathan L., et al. "The M5 simulator: Modeling networked systems." IEEE Micro 4 (2006): 52-60.
[15] Martin, Milo MK, et al. "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset." ACM SIGARCH Computer Architecture News 33.4 (2005): 92-99.
[16] Skadron, Kevin, et al. "Temperature-aware microarchitecture: Modeling and implementation." ACM Transactions on Architecture and Code Optimization (TACO) 1.1 (2004): 94-125.
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embedded benchmark suite." Workload Characterization, 2001. WWC-4. 2001
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Computer Architecture News 34.4 (2006): 1-17.
[20] ODROID-XU+E.
http://www.hardkernel.com/main/products/prdt_info.php?g_code=G1374633630
79
[21] Samsung Exynos 5410 Octa.
http://chip-architect.com/news/Apple_A7_Samsung_5410.jpg
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