臺灣博碩士論文加值系統

非揮發性記憶體（NVM），已開發超過45年並廣泛使用於各類的電子產品。在各種的非揮發性記憶體中，罩幕式可編程唯讀記憶體（Mask ROM）是一個在世界上最便宜的非揮發性記憶體。Mask ROM被廣泛使用於存儲設備，在關閉電源後能夠永久保存資料。而EEPROM，則是目前增長最快的一種非揮發性記憶體產品。本論文提出一種新型的n通道MOSFET具有一個電晶體可儲存兩位元的記憶容量,其使用閘極與源極間之非重疊植入區（NOI）做為Mask ROM和EEPROM的應用。 NOI Mask ROM可以使用輕摻雜汲極（LDD）植入做為編碼。這個簡單的編碼方式是與代工CMOS製程完全兼容。本NOI Mask ROM的特點，包括一個電晶體可儲存兩，基底效應的影響，熱載子的影響和陣列佈局進行研究。通過使用相同的陣列佈局和讀出電路，其電性曲線顯示NOI Mask ROM和NOI EEPROM之間的可以很容易的相互轉換，不需額外的製程與光罩。

Non-volatile Memory (NVM) has been developed and improved in past years, and recently it has been received much attention in mobile or portable applications, such as mobile phones, smart cards and digital camera. First, the history of the Non-volatile Memory (NVM) and the concept of the NVM are introduced. And the typical NVMs, such as EPROM, EEPROM, flash memory are also introduced. However, among various Non-volatile memory types, Mask programmable read-only-memories (Mask ROMs) are one of the cheapest memories. Mask ROMs are widely used memory devices capable of storing permanently information. This thesis presents a novel n-channel MOSFETs with two-bits-per-transistor and gate-to-drain non-overlap implantation (NOI) schemes for Mask ROM and EEPROM applications. The NOI mask ROM can be coded by using the lightly doped drain (LDD) implantation mask and the related processes. This simple coding scheme is fully compatible with industrial CMOS processing. The characteristics of this NOI mask ROM, including two-bit-per-transistor operation, body effect, hot carrier impact and array layouts are investigated. By sharing the same array layout and readout circuit, the potential of NOI devices’ seamless migration between the mask ROM and EEPROM functions are also demonstrated.

Chapter 1 Introduction of Nonvolatile Memory 1
1-1. Introduction of Nonvolatile Memory (NVM) 1
1-2. Objective 3
1-3. Organization of this thesis 4
Chapter 2 Overview of Mask Read Only Memories 7
2-1. Introduction to Mask Read Only Memories 7
2-2. Mask ROM Operation Mechanism 7
2-2-1. Diffusion ROM 9
2-2-2. Implantation Programmed ROM or Flat-cell ROM 10
2-2-3. Contact ROM and Via ROM 12
2-3. NOI Mask ROM 12
2-3-1. Fabrication Process Flow 14
2-3-2. NOI Mask ROM Programming 15
2-3-3. NOI Mask ROM Reading 16
2-4. Summary 19
Chapter 3 The Evaluation of Structure of Charge Storage Type Electric Alterable Nonvolatile Memories 36
3-1. Review of Charge-based Electric Alterable NVMs 36
3-1-1. Charge Trapping Nonvolatile Memory (SONOS) 38
3-1-2. Recent SONOS develop Trends 38
3-2. NOI EEPROM 40
3-2-1. NOI EEPROM Programming 41
3-2-2. NOI EEPROM Erasing 41
3-2-3. NOI EEPROM Reading 42
3-3. Summary 44
Chapter 4 Non-overlapped Implantation Mask ROM Device 54
4-1. NOI Mask ROM Device Characteristics 54
4-2. Effects of Body Bias in Mask ROM Device 56
4-3. Spacer Length Effect and Array Layout 58
4-4. Drain Stress and Hot Carrier Effect 59
4-5. Summary 60
Chapter 5 Non-overlapped Implantation EEPROM Device 72
5-1. NOI EEPROM Two Bits/Cell Operation Principle 72
5-2. NOI EEPROM Device Characteristics 73
5-3. NOI EEPROM Reliability 75
5-4. Summary 78
Chapter 6 Converting Electrical Alterable ROM to Mask ROM 88
6-1. NOI EPROM to NOI Mask ROM 89
6-2. Read-out Window Improvement 90
6-3. Summary 92
Chapter 7 Conclusions and Recommendations for Future Work 100
7-1. Conclusions 100
7-2. Recommendations for Future Work 101
References 102
Publication List 110

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