臺灣博碩士論文加值系統

隨著半導體製程技術的快速發展，以及電子產品往系統單晶片(System on Chip, SoC)的趨勢發展，使得晶片設計的工作日益複雜。因此，透過設計及重複的使用矽智財(Silicon Intellectual Property, SIP)來完成晶片設計，將有效加速設計時程及節省成本。
本論文的製程技術是使用台積電0.35μm CMOS 2P4M來完成電路模擬及晶片的實體佈局。論文中首先完成優先編碼器IP，基於優先編碼器IP完成了二個適用於高速度操作的互補式算術運算電路，分別是比較器及增量器 / 減量器。在加法器的電路設計上，主要是採用「多階層摺疊」及「對角線前傳」等兩種設計技巧。在乘法器的部分，設計一個具有自動補數偵測功能的串-並乘法器。經由Hspice的電路模擬及晶片的量測結果，顯示優先編碼器、加法器、乘法器、比較器及增量器 / 減量器，在性能的表現上均優於傳統式電路。

Due to the rapid development of semiconductor fabrication technique and the trends of System-on-chip-based (SoC-based) electronic products, the integrated circuit design becomes more and more complicated. Therefore, the reusable Silicon-intellectual-property (SIP) is desired, because it could shorten a great deal of design time and cost.
This thesis is considered in Cadence environment for achieving pre- layout / post-layout simulation based on 0.35μm CMOS 2P4M process of TSMC. First, the priority encoder IP design is performed, then based on this encoder IP, both high-speed comparator and incrementer/decrementer are realized. Besides, the pre-layout / post-layout design of an adder is implemented by the use of multilevel folding and diagonal forwarding techniques. Finally, the serial-parallel multiplier with automatic complement detection is proposed. From the results of Hspice simulation and chip testing, the suggested priority encoder, adder, multiplier, comparator, and incrementer/ decrementer show the pretty better performance than that of traditional circuit scheme.

第一章 緒論 1
1.1 研究動機 1
1.2 數位訊號處理器的特性及應用 2
1.3 論文簡介 3
第二章 互補式金氧半的功率消耗及特性分析介紹 4
2.1 功率消耗 4
2.1.1 動態功率消耗( Dynamic Power Dissipation ) 4
2.1.2 漏電流( Leakage Current ) 5
2.1.3 短路電流( Short Circuit Current ) 7
2.2 動態CMOS電路及靜態CMOS電路的特性分析比較 11
2.2.1 雜訊邊界( Noise Margin ) 12
2.2.2 電荷分享( Charge Sharing ) 14
第三章 互補式金氧半算術運算電路的分析設計 16
3.1 優先編碼器( Priority Encoder ) 16
3.1.1 簡介 16
3.1.2 雙層及三層前瞻式架構 18
3.1.3 優先編碼器模擬結果 23
3.2 加法器( Adder ) 27
3.2.1 簡介 27
3.2.2 靜態式架構 28
3.2.3 動態式架構 30
3.2.4 加法器模擬結果 33
3.3 乘法器( Multiplier ) 37
3.3.1 簡介 37
3.3.2 改良的乘法器架構 38
3.3.3 乘法器模擬結果 43
3.4 比較器( Comparator ) 47
3.4.1 簡介 47
3.4.2 以減法器為架構 48
3.4.3 以優先編碼器為架構 50
3.4.4 比較器模擬結果 55
3.5 增量器 / 減量器( Incrementer / Decrementer ) 59
3.5.1 簡介 59
3.5.2 以優先編碼器為架構 60
3.5.3 增量器 / 減量器模擬結果 64
第四章 晶片的設計流程及量測結果 68
4.1 設計流程 68
4.2 量測結果 69
第五章 結論 73
參考文獻 74
附錄: 口試委員意見修正 78

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