臺灣博碩士論文加值系統

本論文致力於三端與四端多閘指元件之設計研究，包括精確萃取本質寄生RLC之創新方法以及如何建立準確的本質MOSFET模型用於高頻元件特性與雜訊模擬，且進一步應用於奈米CMOS射頻電路設計。其中閘極電阻(Rg)、源極電阻(RS)、閘極側壁與閘指端之邊緣雜散電容(Cof and Cf(poly-end))，已成為關鍵性的本質寄生RC參數，對於高頻元件效能以及射頻雜訊有顯著影響，並且針對傳統萃取方法運用於三端與四端多閘指元件，帶來諸多嚴重挑戰。首先，本論文之創新工作為建立新的萃取流程，運用於三端與四端多閘指元件，以精確決定本質寄生源極與汲極電阻(Rs,int 與 Rd,int)以及通道電阻(Rch)。應用此方法於等效電路模型分析，能夠準確預測在VDS=0情況下，閘極到源極/汲極電容的非對稱性，其機制深受本質寄生源極與汲極電阻 (Rs,int 與 Rd,int)以及通道電阻(Rch) 之影響。
接著，將提出新式方法及解析模型以精確萃取閘極電阻 (Rg)，並且預測到本質寄生源極與汲極電阻(Rs,int 與 Rd,int)經由本質閘極到源極/汲極電容耦合效應，對Rg@Y-method產生之顯著影響。再者，本論文提出創新的結構稱為多閘指場效元件，可以從高頻量測中精確性地直接萃取閘極側壁與閘指端之邊緣雜散電容(Cof 與 Cf(poly-end))，不需藉由三維傳輸線RC模擬如Raphael。上述創新結構與方法有助於萃取具有複雜佈局效應的本質寄生RC參數，並搭配本實驗專有之高精確元件參數萃取方法(美國專利 8,691,599 B2)為基礎，可以建立真實的本質MOSFET模型，並驗證於三端和四端多閘指元件，能夠準確預測佈局效應以及靈敏反應製程變異所產生之lot-to-lot與die-to-die統計分佈中元件參數之差異。
本論文所建立之真實本質MOSFET模型已廣泛驗證於三端和四端多閘指元件，能夠準確模擬高頻元件特性如Y參數。此外，上述本質元件參數與本質寄生RLC代入解析模型，能夠準確預測高頻性能如fT和fMAX，並且藉以實現佈局最佳化。其中一項重要發現和結論是，四端多閘指MOSFET的優點為具有足夠的自由度，得以應用於各種電路結構設計，如共源極、共閘極和共汲極以及各式基極偏壓。但是，也同時產生致命缺點，如Rs,int和Ls,int的大幅增加而造成高頻性能fT和fMAX的顯著劣化，明顯低於三端多閘指元件之高頻性能。綜觀上述研究成果，主要的貢獻乃是為高頻模擬和設計提供一新的且準確有效的解決方案以進行最佳化設計，而不須依賴BSIM-4在特定的元件佈局下所局限的可用範圍，以及極其有限之準確性。
最後，藉由結合真實的本質MOSFET元件模型以及本實驗室已驗證完成之損耗基板模型(lossy substrate model)，得以建立完整的等效電路模型，以準確模擬量測所得且未經去寄生效應之高頻S參數、Y參數以及雜訊參數。再者，損耗基板去寄生效應方法(lossy substrate deembedding method)，可應用於三端和四端多閘指MOSFET以準確萃取其本質高頻雜訊。相較於傳統採用之雜訊相關矩陣(noise correlation matrix)來萃取本質高頻雜訊的方法所存在的變異過大問題，此損耗基板去寄生效應方法不僅能有效降低變異，還能準確反應出本質高頻雜訊的佈局相關效應，來達到多閘指MOSFET最佳化設計以運用於低雜訊電路設計。

In this thesis, an extensive investigation has been performed on the three- and four-terminal (3T and 4T) multi-finger nMOSFETs for precise extraction of intrinsic parasitic RLC and development of truly accurate intrinsic MOSFET model aimed at high frequency and RF noise simulation for nano-CMOS RF circuits design. Gate resistance (Rg), source resistance (Rs,int), and gate sidewall as well as finger-end fringing capacitances (Cof and Cf(poly-end)) appear as most important intrinsic parasitic RC with critical impact on high frequency performance and RF noise, and bring tough challenges to the conventional extraction methods when applied to 3T and 4T multi-finger MOSFETs. For the first time, a new extraction flow has been established for precise determination of the intrinsic parasitic source and drain resistances (Rs,int and Rd,int) and channel resistance (Rch) in 3T and 4T multi-finger MOSFETs and enable accurate prediction of the asymmetric gate to source/drain capacitances, i.e. Cgs≠Cgd at VDS=0 with critical dependence on Rs,int, Rd,int, and Rch. Afterwards, a new method and analytical model have been derived for accurate extraction of Rg and prediction of Rg@Y-method incorporating the Rs,int and Rd,int coupled through the intrinsic gate to source and drain capacitances (Cgs,i and Cgd,i). In this thesis, one more innovation creates new structures, namely multi-finger field devices for direct and precise extraction of Cof and Cf(poly-end) from high frequency measurement, without resort to 3-D interconnect RC simulation like Raphael. The mentioned innovations lead to successful extraction of intrinsic parasitic RC with complicated layout dependence and the integration with intrinsic device parameters determined by our proprietary high precision device parameters extraction method (US patent 8,691,599 B2) can realize the actual intrinsic MOSFET model for 3T and 4T multi-finger MOSFETs with proven accuracy for layout dependent effects and sensitivity to lot-to-lot and die-to-die variations.
The actual intrinsic MOSEFT model has been extensively verified and the accuracy is proven by good agreement with high frequency Y-parameters after openM1 and shortM1 deembedding for 3T and 4T nMOSFETs with various multi-finger layouts. Furthermore, the intrinsic device parameters and parasitic RLC with proven accuracy, when applied to analytical models can reach accurate prediction of the high frequency performance like fT and fMAX associated with various multi-finger layouts and facilitate layout optimization. One of the important findings and conclusions is that 4T multi-finger MOSFETs with sufficient freedom for various circuit topologies like common source, common gate, and common drain (CS, CG, and CD) under various body biases, generally suffer significant degradation of fT and fMAX due to drastic increase of Rs,int and Ls,int. The mentioned achievements provide a useful and efficient solution for high frequency simulation and design, without resort to BSIM-4 with limited accuracy for specified sample layouts.
Finally, the actual intrinsic MOSFET models can be further integrated with our proprietary lossy substrate model to build up a full equivalent circuit model, which can accurately simulate the high frequency S-, Y- and noise parameters, prior to deembedding. Furthermore, the lossy substrate deembedding method can be applied to both 3T and 4T multi-finger MOSFETs as a reliable solution for accurate extraction of intrinsic RF noise, which can eliminate the problems of conventional noise correlation matrix method and successfully identify the layout dependent effects in the truly intrinsic RF noise for multi-finger MOSFETs optimization aimed at low noise circuits design.

Chinese Abstract i
Abstract iii
致謝 vi
Contents vii
Figure Captions x
Table Captions xxxv
Chapter 1 Introduction 1
1.1 Research Motivation 1
1.2 Overview 2
Chapter 2 Fundamental Theory and Measurement Techniques 4
2.1 S-parameter Measurement and De-embedding 4
2.1.1 Two-Port Network Analyzer Measurement Techniques 4
2.1.2 Two Steps De-embedding Method 5
2.2 Thermal Noise Theory and Measurement Method 7
2.2.1 Thermal Noise Sources 7
2.2.2 Noise Figure and Parameters 8
2.2.3 High Frequency Noise Measurement System and Method 9
2.2.3.1 System Configuration 9
2.2.3.2 System Calibration 10
Chapter 3 Parasitic RC and Device Parameters Extraction in Multi-Finger n-MOSFETs for High Frequency Simulation 12
3.1 Multi-finger MOSFETs Layouts 12
3.2 I-V Characteristics (IDS, gm, and VT) with Layout Dependent Effects in Multi-finger nMOSFETs 15
3.3 Source Resistance Extraction by TML Model and LPE and Verification of Layout Dependent Effects 38
3.4 3-D Fringing Capacitance Simulation and Analysis by Raphael 43
3.5 Device Parameters and Effective Mobility for 3T and 4T Multi-Finger n-MOSFETs - Layout Dependent Effects and Lot-to-Lot Variations 54
Chapter 4 New Method for Gate and Source/Drain Resistances Extraction in Multi-Finger MOSFETs for High Frequency Simulation 65
4.1 Small Signal Equivalent Circuit Model under Cold Device Bias Condition and Parameters Extraction 65
4.2 A Modified Intrinsic MOSFET Model and New Method for Intrinsic Channel and Parasitic Resistances Extraction 78
4.3 Actual Intrinsic MOSFET Model for Accurate Simulation of High Frequency and Layout Dependence in 3T and 4T Multi-finger nMOSFETs 102
4.4 Gate Resistance Extraction and Modeling in Multi-finger Poly TML 132
Chapter 5 High Frequency Characteristics and Layout Dependent Effects in 3T and 4T Multi-finger n-MOSFETs 139
5.1 High Frequency Performance Parameters Extraction and Analysis- Layout Dependent Effect and Lot-to-Lot Variations 139
5.2 High Frequency Performance in 3T and 4T Multi-finger n-MOSFETs 148
5.2.1 Cut-Off Frequency fT – layout dependent effects and lot-to-lot variation 148
5.2.2 Maximum Oscillation Frequency fMAX - layout dependent effects and lot-to-lot variation 158
Chapter 6 Small Signal Equivalent Circuit Model for High Frequency Performance and Noise Simulation in 3T and 4T Multi-finger n-MOSFETs 172
6.1 Lossy Substrate RLC Network Model 172
6.2 Improved MOSFET Model with Intrinsic Parasitic RLC 179
6.3 High Frequency Simulation for 3T and 4T Multi-finger n-MOSFETs in Equivalent Circuit Models 184
6.3.1 High Frequency Simulation for 3T and 4T Intrinsic n-MOSFET after De-embedding –Actual intrinsic MOSFET Model 184
6.3.2 High Frequency Simulation for 3T and 4T n-MOSFET before De-embedding – Full Equivalent Circuit Models 196
6.4 High Frequency Noise Analysis and Simulation for 3T and 4T Multi-finger n-MOSFETs 204
6.4.1 High Frequency Noise Parameters in 3T and 4T Multi-finger n-MOSFETs – Layout Dependent Effects 204
6.4.2 Noise Correlation Matrix Method for High Frequency Noise De-embedding 208
6.4.3 High Frequency Noise Simulation by Equivalent Circuit Models Before and After Deembedding 214
6.4.4 3T and 4T Multi-finger n-MOSFETs Layout Optimization Strategies for Low Noise Design 230
Chapter 7 Conclusions and Future Work 233
7.1 Conclusions 233
7.2 Future Work 235
References 236

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