臺灣博碩士論文加值系統

本論文提出應用於第五代通訊系統中，於接收器端將基頻訊號放大的可調變增益式放大器(Variable Gain Amplifier, VGA)以及將雜訊和頻帶外訊號濾除的濾波器(Filter)，配合後端的類比數位轉換器(Analog-to-Digital Converter, ADC)，將處理過後的類比訊號藉由類比數位轉換器轉換成數位訊號交給後續的數位電路處理，完成第五代通訊系統的基頻接收前端電路(Baseband Front-End Rx Circuit)。本論文著重於可調變增益放大器以及濾波器的部分。
ar
由於第五代通訊系統要求的頻寬較高，因此選擇採用轉導電容式濾波器(Gm-C Filter)以達到要求，比起交換式電容濾波器(Switched-Capacitor Filter)以及主動電阻電容濾波器(Active-RC Filter)，轉導電容式濾波器更適合用在高速的系統上。但是其最主要的缺點為線性度(Linearity)較差的問題，所以如何改善線性度成為了我們所要著重的地方。
ar
可調變增益放大器則基於轉導電容式濾波器的架構，利用調整電阻值的大小來達成調變增益的目的。利用此可調變增益放大器以及轉導電容式濾波器，實現應用於第五代通訊系統，截止頻寬為1.5625 GHz並且以1 dB為單位調整達到8 dB至40 dB增益的三階(Third-order)可調變增益濾波系統，並利用直流偏置消除(DC-Offset Cancellation, DCOC)電路，採用負回授(Negative Feedback)原則，比較正輸出和負輸出兩端電壓，放大其誤差並回授至第一級放大器以減少偏置(Offset)所帶來的非理想效應。此設計以台積電28 nm CMOS製程來設計，所占面積為 198.07 x 90.88 um$^{2}$。電路主要操作在1 V電壓，唯有輸出級因為輸出振福要求為+/- 400 mV而使用1.5 V電壓，在輸入訊號為5MHz至1.5625 GHz，當振幅為+/- 150 mV時，其無雜散動態範圍(Spurious-Free Dynamic Range, SFDR)可以達到47 dB以上，信納比(Signal-to-(Noise+Distortion)-Ratio, SNDR)為36 dB以上，總諧波失真(Total Harmonic Distortion, THD)為 -38 dB以上，消耗功率為48mW。

For the fifth generation (5G) communication system, we use variable gain amplifier (VGA) to amplifier the baseband signal at receiver and use filter to filter out noise and any other signals which are not in the signal band. After that, we use analog-to-digital converter (ADC) to convert analog signal to digital signal for digital circuits and complete the baseband front-end receiver circuit of the fifth generation communication system. This paper is about VGA and filter.
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Due to the specification of bandwidth is wider in the fifth generation communication system, we use Gm-Miller-C filter instead of switch-capacitor filter and active-RC filter to reach the specification. The Gm-Miller-C filter is more suitable for high speed system, but the main disadvantage is the worse linearity. It is the most important part for us to improve the linearity.
ar
The VGA structure is based on the design of Gm-Miller-C filter and we can change the value of resistors to get programmable voltage gain. We applied the VGA and Gm-Miller-C filter as a third-order baseband chain in the fifth generation communication system and get 1.5625 GHz -3dB frequency also we can change the voltage gain from 8 dB to 40 dB for each 1 dB step. Also, we use DC-offset cancellation technique with negative feedback topology. Comparing the positive and negative output voltage and feedback to the first stage after amplifier the mismatch to reduce the impact of offset.
ar
This design use TSMC 28 nm CMOS process and the layout area is 198.07 x 90.88 um$^{2}$. the main circuit operate at 1 V and 1.5 V for the last stage to meet the output swing of +/- 400 mV. For the input signal bandwidth is from 5 MHz to 1.5625 GHz and input swing is +/- 150 mV, we can get SFDR is more than 47 dB, SNDR is more than 36 dB and THD is more than -38 dB. The whole design consumes 48 mW.

摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
誌謝. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
一、緒論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 論文組織. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
二、運算轉導放大器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 高線性度運算轉導放大器的基本架構. . . . . . . . . . . . . . . . . . . . . 4
2.2.1 差動輸入(Differential Input) . . . . . . . . . . . . . . . . . . . . . . 5
2.2.2 源極退化(Source Degeneration) . . . . . . . . . . . . . . . . . . . . 6
2.2.3 翻轉電壓跟隨器(Flipped Voltage Follower) . . . . . . . . . . . . . . 8
2.2.4 超級源極跟隨器(Super Source Follower) . . . . . . . . . . . . . . . 9
2.3 使用的轉導架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
三、轉導電容式濾波器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 基本的轉導積分器設計. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 積分器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2 全差動積分器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.3 米勒轉導式電容積分器(GmMillerC
integrator) . . . . . . . . . . . 15
3.2.4 雙二階濾波器架構(Biquad) . . . . . . . . . . . . . . . . . . . . . . 16
3.3 使用的濾波器架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
iv
四、可調變增益放大器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 基本的可調變增益放大器架構. . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2.1 電流分配架構(Current divider) . . . . . . . . . . . . . . . . . . . . . 21
4.2.2 源極耦合對(Sourcecoupled
pair) . . . . . . . . . . . . . . . . . . . . 21
4.2.3 源極衰退(Source degeneration) . . . . . . . . . . . . . . . . . . . . . 22
4.2.4 放大器電阻網路回授(resistornetwork
feedback) . . . . . . . . . . . 22
4.3 使用的可調變增益放大器架構. . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.1 電阻陣列與開關. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
五、接收器基頻鏈. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2 接收器基頻鏈的介面. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3 基頻鏈方塊圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 佈局(Layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
六、晶片佈局與模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1 晶片佈局圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 線性度參數簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1 SNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.2 THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.3 SNDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.1 頻率響應. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3.2 快速傅立葉轉換(FFT) . . . . . . . . . . . . . . . . . . . . . . . . . 35
七、結論與未來展望. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
自傳. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

[1] Y. Tsividis, Z. Czarnul, and S. C. Fang, “Mos transconductors and integrators with high
linearity,” Electronics Letters, vol. 22, no. 5, pp. 245–246, February 1986.
[2] A. Lewinski and J. SilvaMartinez,
“A highfrequency
transconductor using a robust nonlinearity
cancellation,” IEEE Transactions on Circuits and Systems II: Express Briefs,
vol. 53, no. 9, pp. 896–900, Sep. 2006.
[3] Z. Y. Chang, D. Haspeslagh, J. Boxho, and D. Macq, “A highly linear cmos gmc
bandpass
filter for video applications,” in Proceedings of Custom Integrated Circuits Conference,
May 1996, pp. 89–92.
[4] E. SanchezSinencio
and J. SilvaMartinez,
“Cmos transconductance amplifiers, architectures
and active filters: a tutorial,” IEE Proceedings Circuits,
Devices and Systems, vol.
147, no. 1, pp. 3–12, Feb 2000.
[5] J. RamirezAngulo,
R. G. Carvajal, A. Torralba, J. Galan, A. P. VegaLeal,
and J. Tombs,
“The flipped voltage follower: a useful cell for lowvoltage
lowpower
circuit design,”
in 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.
02CH37353), vol. 3, May 2002, pp. III–III.
[6] D. K. Shedge, D. A. Itole, M. P. Gajare, and P. W. Wani. (2013, June) Analysis and design
of cmos source followers and super source follower.
[7] A. Leuciuc, “A wide linear range lowvoltage
transconductor,” in 2003 IEEE International
Symposium on Circuits and Systems (ISCAS), vol. 1, May 2003, pp. I161–164.
[8] R. Schaumann and M. E.Van Valkenburg, Design of Analog Filter. New York:: New
York:Oxford University Press, Inc., 2001.
[9] ChengChung
Hsu and JiehTsorng
Wu, “A highly linear 125mhz
cmos switchedresistor
programmablegain
amplifier,” IEEE Journal of SolidState
Circuits, vol. 38, no. 10, pp.
1663–1670, Oct 2003.
38
[10] M. Schtzen, The Volterra and Wiener Theories of Nonlinear Systems. New York: Wiley,
1980.
[11] M. Elmala, B. Carlton, R. Bishop, and K. Soumyanath, “A highly linear filter and vga
chain with novel dcoffset
correction in 90nm digital cmos process,” in Digest of Technical
Papers. 2005 Symposium on VLSI Circuits, 2005., June 2005, pp. 302–303.
[12] C. Wu, J. Hsieh, C. Wu, Y. Cheng, C. Wu, and S. Lu, “An 1.1 v 0.1–1.6 ghz tunablebandwidth
elliptic filter with 6 db linearity improvement by precise zero location control
in 40 nm cmos technology for 5g applications,” in 2017 IEEE International Symposium
on Circuits and Systems (ISCAS), May 2017, pp. 1–4.
[13] F. Houfaf, M. Egot, A. Kaiser, A. Cathelin, and B. Nauta, “A 65nm cmos 1to10ghz
tunable continuoustime
lowpass
filter for highdatarate
communications,” in 2012 IEEE
International SolidState
Circuits Conference, Feb 2012, pp. 362–364.
[14] N. Sabatino, G. Minoia, M. Roche, D. Baldi, E. Temporiti, and A. Mazzanti, “A 5thorder
gmc
lowpass
filter with ±3accuracy and 220mhz to 3.3ghz tuningrange
in 28nm lp
cmos,” in ESSCIRC 2014 40th
European Solid State Circuits Conference (ESSCIRC),
Sep. 2014, pp. 351–354.