臺灣博碩士論文加值系統

由於浮動式閘極快閃記憶體無法滿足元件微縮發展的趨勢，因此利用電荷陷阱式快閃記憶體式取代浮動式閘極結構元件是未來發展的趨勢。然而傳統SONOS元件以氮化矽做為電荷儲存層的結構，在發展到次微米以下時就無法再以降低穿隧氧化層厚度的方式來提升元件操作效率，因此便引進了高介電材料來取代傳統ONO結構以提升元件操作機制。而在通道介面處磊晶一層矽化鍺，藉由能帶工程提升操作載子的能量，希望藉此材料的應用達到較高的元件操作效率。
本論文的研究方向主要分為下列三項：
(1) 藉由改變矽化鍺通道的鍺含量，來調變矽化鍺通道介面處的能隙，改變穿隧載子的穿隧能量，來比較不同條件對於元件操作效率上的改善。
(2) 藉由改變矽化鍺通道的厚度，以及堆疊方式，來調變矽化鍺通道介面處的穿隧範圍以及對於單晶矽覆蓋層的應力問題，來比較不同條件對於元件操作效率上有什麼影響。
(3) 改變矽化鍺通道上方的單晶矽覆蓋層厚度，藉此改善矽化鍺通道與穿隧氧化層之間的介面特性，觀察用此方式對於元件電性上有改善與影響。
而經由實驗結果發現，引進矽化鍺通道的記憶體元件，相較於傳統矽基板在操作效率上有明顯的提升，並發現在固定單晶矽覆蓋層厚度前提下，鍺含量越低，以及矽化鍺通道厚度越薄，元件操作效率會越來越好，而改變單晶矽覆蓋層厚度以求改進介面特性部份，隨著單晶矽覆蓋層厚度增加，元件操作效率也會有隨之變好的趨勢。

摘要…………………………………………………………………………………..i
致謝………………………………..………………………………………….……..ii
目錄 ………………………………….…………………………………….………iv
圖目錄……………………………………………………...……………….……..vii
表目錄 …………………………………………….……………………….…..…xii
第一章 序論………………………………….……………………………………1
1.1 前言…………………………………………………………..……………1
1.2 快閃記憶體面臨問題……………………………………………………1
1.3 電荷陷阱式快閃記憶體的結構及其優缺點……………………….…2
1.4 研究目的…………………………………………………………………4
1.5 各章摘要………………………………………………………………….6
第二章 快閃記憶體元件操作方法 ………………………………….……….13
2.1 寫入與擦拭方法…………………………………………….……….…13
2.1.1 CHEI通道熱電子注入寫入……………………..……………13
2.1.2 CHISEL初始通道載子引發二次電子注入寫入…………13
2.1.3 BBHE帶對帶穿隧引發熱電子寫入…………………………14
2.1.4 FN穿隧寫入 ………………………………………..…………15
2.1.5 FN穿隧抹除 ……………………………………………..……16
2.2 耐力………………………………………………………………………16
2.3 干擾………………………………………………………………………17
2.4 電荷保持………………………………………………………………...18
第三章 實驗規劃及元件製程……………………………………………….…30
3.1 實驗規畫………………………………………………………………30
3.2 電容元件製程……………………………………………..……………31
3.2.1 電容前段製程…………………………………………………31
3.2.2 矽化鍺通道磊晶製程……………………….………………31
3.2.3 成長穿隧氧化層………………………………………………32
3.2.4 沉積電荷儲存層以及阻擋層……………………..…………32
3.3.5 電容後段製程…………………………………………………33
第四章 矽化鍺通道中調變不同鍺含量對電荷陷阱式快閃記憶體特性的
影響……………………………………….………………………….…39
4.1 研究背景與目的……………………………………………………..…39
4.2 實驗規劃及製程………………………………………………………40
4.3實驗結果與討論…………………………………………………………41
4.3.1 矽化鍺通道對於不同鍺含量的效應…………………...…..41
4.3.2 純鍺通道的效應………………………………………………44
4.4 結論………………………………………………………………………47
第五章 矽化鍺通道中調變不同矽化鍺通道厚度對電荷陷阱式快閃記憶
體特性的影響……………………………………..……………………67
5.1 研究背景與目的…………………………………………………..……67
5.2 實驗規劃及製程……………………………………………………..…68
5.3 實驗結果與討論………………………………………………..………69
5.3.1不同矽化鍺通道厚度的效應…………………………………69
5.3.2堆疊式矽化鍺通道的效應……………………………………72
5.4 結論………………………………………………………………………74
第六章 矽化鍺通道中調變不同單晶矽覆蓋層厚度對電荷陷阱式快閃記
憶體特性的影響………………………………………………..……89
6.1 研究背景與目的………………………………………………………89
6.2 實驗規劃及製程……………………………………………………..…90
6.3 實驗結果與討論………………………………………………………91
6.3.1對於Ge11% 200�眭熙q道不同單晶矽覆蓋層厚度的效應..91
6.3.2對於Ge30% 400�眭熙q道不同單晶矽覆蓋層厚度的效應..94
6.3.3對於Ge30% 600�眭熙q道不同單晶矽覆蓋層厚度的效應..96
6.4 結論………………………………………………………………………98
第七章 結論與建議……………………………………………………………120
7.1 結論………………………………………………………………….…120
7.2 建議…………………………………………………………………….121
參考文獻……………………………………………………………………….…122

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