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研究生:張晏碩
研究生(外文):Yen-Shuo Chang
論文名稱:低電壓操作共模前饋與三次諧波消減轉導放大器之設計
論文名稱(外文):On the Design of a Low Voltage Pseudo Differential Operational Transconductance Amplifier with Common Mode and HD3 Feed Forward Cancellation Technologies
指導教授:蕭敏學蕭敏學引用關係
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:76
中文關鍵詞:虛擬差動共模前饋三次諧波轉導放大器
外文關鍵詞:HD3Pseudo DifferentialCMFFOTA
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本論文提出一低電壓操作且高線性度轉導放大器,其電路以虛擬差動輸入為主體,其動態操作範圍比傳統轉導放大器優良。運用Wide-Swing cascode 架構讓電路可操作在1.2V下正常工作,並有 11.8 MΩ 的輸出阻抗,必v的消耗相當節省,總體必v消耗為 75.8 μW (1K Hz) 。本論文使用兩種技術,其一為共模信號前饋(CMFF)技術,用此技術來消除虛擬差動所產生的共模輸出,使得共模拒斥比(Common Mode Rejection Ratio, CMRR) 得以提升為 68.6dB 。另一技術為三次諧波前饋 (Third-Order Harmonic Distortion Feed Forward, HD3-FF),用來提升電路線性度,三次諧波為 -66.6dB。本研究主題之實現使用TSMC 0.18μm CMOS的製程技術,使用面積為0.69x0.38 mm2。
A pseudo differential Operational Transconductance Amplifier (OTA) has been proposed in this research. This OTA can operate at low supply voltage with high linearity. Here, we use two technologies, one of them is common mode feed forward and the other is HD3 feed forward. Simulation results show that the common mode rejection ratio (CMRR) is 68.6dB and third harmonic distortion (HD3) is -66.6dB. This OTA consumes 75.8μW for the power dissipation. The chip has been manufactured in a 0.18μm-CMOS technology. The chip area is 0.69x0.38 mm2.
中文摘要 i
英文摘要(Abstract) ii
致謝 iii
目錄 iv
圖目錄 vi

第一章 緒論 1
1.1研究動機 1
1.2論文架構 3

第二章 傳統全差動轉導放大器 5
2.1 全差動模式轉導放大器 6
2.1.1 全差動模式轉導放大器基本特性 6
2.1.2 全差動模式轉導放大器線性度推導 8
2.2 虛擬差動轉導放大器 12
2.2.1 虛擬差動轉導放大器基本特性 12
2.2.2 虛擬差動轉導放大器線性度推導 13
2.3電路非線性產生原因與分析 15

第三章 共模前饋技術 (Common Mode Feed Forward)與三次諧波失真消減技術(Third-Order Harmonic Distortion Feed Forward) 21
3.1共模拒斥比定義 21
3.2共模前饋 (Common Mode Feed Forward) 21
3.3 三次諧波消減技術(Third-Order Harmonic Distortion Feed Forward,HD3-FF ) 24
3.4 提升輸出阻抗之虛擬差動轉導放大器 28

第四章 低電壓操作共模前饋與三次諧波消減之轉導放大器 31
4.1 所提出OTA相關特性 31
4.2 低電壓操作共模前饋與三次諧波消減之轉導放大器 31
4.2.1電路原理 31
4.2.2電路小訊號推導 34
4.2.3 OTA頻域響應的分析 39

第五章 低電壓共模前饋與三次諧波消減轉導放大器模擬 41
5.1 轉導放大器的輸入特性 42
5.2 轉導放大器的失真 44
5.3 放大器的頻率響應 48
5.4 轉導放大器的共模拒斥比 49
5.5 轉導放大器的電源拒斥比 50
5.6 轉導放大器的製程變異 51
5.7 相關研究的比較 52

第六章 晶片量測結果 53
6.1 晶片量測的設置 53
6.2 晶片佈局圖與晶像圖 54
6.3 晶片測試電路的設計 55
6.4 晶片量測結果圖形 57
6.4.1基本特性量測 57
6.4.2 晶片輸入信號織T與線性度關係 59
6.5 量測結果比較 62
6.6 量測結果討論 62

第七章 結論 64
參考文獻 66
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