臺灣博碩士論文加值系統

本論文主要在探討薄閘極氧化層於奈米尺度下施加動態應力後所展現的退化及崩潰之行為。過去，有不少文獻指出薄氧化層的退化與崩潰是一種非常局部化的行為，而單一崩潰現象是無法從傳統量測方式中被觀測到的。因此我們必須使用具有奈米等級解析度的量測儀器來分析超薄氧化層單一的崩潰及退化情形。

在本論文中，我們將半導體參數分析儀(Agilent 4156C)與傳導式原子力顯微鏡做結合，再透過半導體參數分析儀高性能的電性量測能力與傳導式原子力顯微鏡的微觀量測能力來進行量測。傳導式原子力顯微鏡的探針針尖與裸露的氧化層直接接觸，取代了傳統金氧半電容的金屬閘極，且探針與氧化層接觸面積極小，大約只有幾十到幾百平方奈米，且側向解析度亦可達幾個奈米的範圍。也就是說我們量測到的將是氧化層本質的退化與崩潰行為。而半導體參數分析儀包含了Agilent 41051模組，使其可提供施加動態應力的能力。

氧化層可靠度研究通常是被執行在直流偏壓條件下，然而在實際的電路中，MOSFET的閘極與汲極經常承受到的是隨時間而變化之偏壓。目前文獻上所探討的交流應力所觀測到的現象，都是在傳統金氧半電容所得到之閘極面積下氧化層平均崩潰資訊。基於我們過去對薄氧化層於奈米尺度直流應力下的了解，在本研究中希望能更進一步得知其在奈米尺度動態應力作用下的特性。

在本論文中，我們透過傳導式原子力顯微鏡施加單極性脈波電壓應力與雙極性脈波電壓應力於二氧化矽氧化層上，其中單極性脈波電壓應力又分為正、負兩種不同之極性。我們觀測流過氧化層電流隨時間變化的情形，亦即量測氧化層電流-時間(I-t)特性圖，並選擇於不同的時間點量測電流-電壓(I-V)特性以較施加不同之動態應力後之異同。我們統計不同頻率動態應力作用下氧化層之崩潰時間，並觀察每個應力對時間相依介電層退化或崩潰的影響。

我們實驗的結果顯示，與直流應力比較單極性脈波應力作用下的氧化層會具有較高的平均崩潰時間，但此崩潰時間會隨頻率的增加而減少。隨著負載週期增加，脈衝應力持續作用於氧化層上的時間也就增加了，故崩潰時間便減少了。在雙極性脈衝應力下，氧化層卻不容易產生硬崩潰，而是有軟崩潰的現象發生；隨著頻率愈大，它的崩潰時間也愈長，當超過某頻率後，崩潰時間卻反而開始縮短了。藉由基值負電壓的改變，我們可以觀察到正向穿隧電流與負向穿隧電流之增減。當基值電壓大小與峰值電壓大小相等時，所觀察到之崩潰時間是最長的。這些我們認為與氧化層中電洞的捕捉與反捕捉有關。

The theme of this thesis mainly focuses on the degradation and breakdown behaviors of thin gate oxide layer subjected to dynamic nanoscale stress. It is known that the degradation and breakdown behaviors of thin oxide are a highly localized phenomenon and unique breakdown event can not be easily detected by using traditional measurement method. Measurement instrument with nanoscale resolution is required to characterize the intrinsic breakdown of thin gate oxide.

By taking advantage of nanoscale measurement capability of conductive atomic force microscopy (CAFM) and the excellent performance in electrical characterization of semiconductor parameter analyzer Agilent 4156C, we combined the two to apply both the unipolar and bipolar pulse waves as electrical stress applied onto the bared thin silicon dioxide films through CAFM tip which acted as the metal gate electrode in the traditional metal-oxide-semiconductor capacitor (MOSC). The contact area between the probe and the oxide layer is about several dozens to several hundred square nanometers, and the lateral resolution could reach a range of several nm. Agilent 41051 module is included in the semiconductor parameter analyzer so that it can output various pulse voltages as the dynamic stress used in this work.

Oxide reliability studies are usually performed under dc bias conditions. However, the gate and drain of a MOSFET always experience time-vary bias in actual circuit. Papers found in the literature that discussed about the behaviors of MOS capacitors under dynamic stress only provides average oxide breakdown information under the gate area.

Although one can find reports about oxide reliability test in which ac stress is applied on MOS devices, none in the literature has addressed the effect of ac stress on the oxide degradation and breakdown behaviors at nanoscale. Based on our past investigations on the reliability of thin oxide layer subjected to dc stress at nanoscale, we explored the nanoscale degradation and breakdown properties of thin gate oxide under dynamic stress in this study.

Unipolar pulse voltages with either polarities as well as bipolar pulse voltages were applied to thin silicon dioxide films through the CAFM tip. During the application of stress, current vs. time (I-t) characteristics of the silicon dioxide films were monitored and the current-voltage (I-V) characteristics were measured at some pre-selected time point so that the time-dependent oxide degradation is understood.

We varied the frequencies as well as duty cycles of the pulse voltages and analyzed the times-to-breakdown. We found that the average time-to breakdown for unipolar stress decreases with increasing frequency and is higher than that for DC stress case. The actual stress time of the pulse signal acting on oxide layer increases with increasing duty cycle, and the average time-to-breakdown is therefore decreases. For oxides under bipolar pulse stress, soft breakdown is observed more frequently than is hard breakdown. The time-to-breakdown for the bipolar case increases with increasing frequency at the initial stage, then it decreases as the frequency is higher than a certain value. We also monitored the changes of forward and the backward tunneling current by changing the base level of the pulse voltages, and noticed that the time-to-breakdown is the longest when |Vhi| = |Vlo|, We attributed this phenomenon to be related to the hole trapping and detrapping in the oxide layer.

第一章 緒論----------------------------------------------------------------------------1
1-1 歷史背景與研究動機---------------------------------------------------------------1
1-2 可靠度分析---------------------------------------------------------------------2
1-2-1 巨觀量測-----------------------------------------------------------------3
1-2-2 微觀量測-----------------------------------------------------------------3
1-2-2 可靠度分析方法------------------------------------------------------------4
1-3 氧化層崩潰機制------------------------------------------------------------------6
1-4 論文架構-----------------------------------------------------------------------7

第二章交流應力下之可靠度研究-----------------------------------------------------------------19
2-1 文獻回顧----------------------------------------------------------------------19
2-2 可靠度現象--------------------------------------------------------------------20
2-2-1 熱電子效應(Hot-electron effect)-----------------------------------------20
2-2-2 閘極氧化層(Gate oxide)--------------------------------------------------22

第三章 實驗程序---------------------------------------------------------------------------33
3-1 樣品製備----------------------------------------------------------------------33
3-2 量測設定----------------------------------------------------------------------33
3-2-1 量測步驟----------------------------------------------------------------34
3-2-2 參數設定----------------------------------------------------------------35

第四章 結果與討論--------------------------------------------------------------------------42
4-1 前言-------------------------------------------------------------------------42
4-2 電流-時間圖之定義---------------------------------------------------------------42
4-3 施加週期性單極性動態方波電壓於氧化層-----------------------------------------------43
4-3-1 正單極性動態方波----------------------------------------------------------43
4-3-2 負單極性動態方波----------------------------------------------------------46
4-3-3單極性應力與崩潰時間-------------------------------------------------------49
4-4 施加週期性雙極性動態方波電壓於氧化層-----------------------------------------------50
4-5 負載週期----------------------------------------------------------------------53
4-6 基值電壓----------------------------------------------------------------------55

第五章 結論與未來展望----------------------------------------------------------------------89
5-1 結論-------------------------------------------------------------------------89
5-2 未來展望----------------------------------------------------------------------91

參考文獻/References----------------------------------------------------------------------92

[1] G. E. Moore, “Cramming More Components onto Integrated Circuits” Electronics, Vol. 38, No. 8, pp. 114-117, Apr. 1965.
[2] G. E. Moore, “Progress in Digital Integrated Electronics” IEDM Tech. Dig., Vol. 21, pp. 11-13, 1975.
[3] G. E. Moore, “Moore’s Law at 40” The Economist print edition, pp. 67-84, Mar. 2005.
[4] International Technology Roadmap for Semi-conductors 2008 Update.
[5] Qiuxia Xu, Xiaofong Duan, He Qian, Haihua Liu, Haiou Li, Zhensheng Han, Ming Liu, and Wenfang Gao, “Hole Mobility Enhancement of pMOSFETs with Strain Channel Induced by Ge Pre-Amorphization Implantation for Source/Drain Extension” IEEE Trans. on Electron Devices, Vol. 27, No. 3, pp. 179-181, Mar. 2006.
[6] Andrea Cester, Salvatore Cimino, Enrique Miranda, Andrea Candelori, Gabriella Ghidini, and Alessandro Paccagnella, “Statistical Model for Radiation-Induced Wear-Out of Ultra-Thin Gate Oxides After Exposure to Heavy Ion Irradiation” IEEE Trans. on Nucl. Sci., Vol. 50, No. 6, pp. 2167-2175, Dec. 2003.
[7] J.Y. Choi, P.K. Ko, and C. Hu, “Hot-Carrier-Induced MOSFET Degradation: AC Versus DC Stressing” Dig. of Tech. Papers. Symp. VLSI Tech., pp. 45-46, May 1987.
[8] T. P. Chen, Stella Li, S. Fung, and K. F. Lo “Interface Trap Generation by FN Injection Under Dynamic Oxide Field Stress” IEEE Trans. on Electron Devices, Vol. 45, No. 9, pp. 1920-1926, Sep. 1998.
[9] Chenming Hu, “Reliability Phenomena Under AC Stress” Microelectron. Reliab., Vol. 38, No. 1, pp. 1-5, Feb. 1998.
[10] Prasad Chaparala, John S. Suehle, Cleston Messick, and Marvin Roush, “Electric Field Dependent Dielectric Breakdown of Intrinsic SiO2 Films Under Dynamic Stress” in Proc. 34th IRPS Conf., pp. 61-66, Apr.- May 1996.
[11] Marc Porti, Montserrat Nafria, and Xavier Aymerich, “Nanometer-Scale Analysis of Current Limited Stresses Impact on SiO2 Gate Oxide Reliability Using C-AFM” IEEE Trans. on Nanotechnology, Vol. 3, No. 1, pp.55-60, Mar. 2004.
[12] C. Julian Chen, “Introduction to Scanning Tunneling Microscopy” Department of Appl. Phys. and Appl. Math. Columbia University, New York, pp. 1-40, 2008.
[13] G. Binnig and Heinrich Rohrer, “Scanning Tunneling Microscopy- from Birth to Adolescence” rev. of Mod. Phys., Vol. 59, No. 3, pp. 615-625, Jul. 1987.
[14] Heiji Watanabe, and Toshio Baba, “Characterization of Local Dielectric Breakdown in Ultrathin SiO2 Films Using Scanning Tunneling Microscopy and Spectroscopy” J. Appl. Phys., Vol.85, No. 9, Page 6704-6710, May 1999.
[15] M.H.Hecht, L.D.Bell, W.J.Kaiser, and F.J.Grunthaner, “Ballistic-Electron-Emission Microscopy Investigation of Schottky Barrier Interface Formation” Appl. Phys. Lett., Vol. 55, No. 8, pp. 780-782, Aug. 1989.
[16] B. Kaczer, and J.P. Peiz, “Ballistic-Electron Emission Microscopy Studies of Charge Trapping in SiO2” J. Vac. Sci. Technol., Vol. 14, No. 4, pp. 2864-2871, Jul. 1996.
[17] G. Binnig, C H. Gerber, E . Stoll, T. R. Albrecht and C. F. Quate “Atomic Resolution with Atomic Force Microscope” Europhys. Lett., Vol. 3, No. 12, pp. 1281-1286, June 1987.
[18] G. Binnig, M. Despont, U. Drechsler, W. Ha‥ berle, M. Lutwyche, and P. Vettigera “Ultrahigh-Density Atomic Force Microscopy Data Storage with Erase Capability” Appl. Phys. Lett., Vol. 74, No. 9, pp. 1329-1331, Mar. 1999.
[19] A. L. Weisenhorn and P. K. Hansma, T. R. Albrecht and C. F. Quate “Force in Atomic Force Microscopy in Air and Water” Appl. Phys. Letter. Vol. 54, No. 26, pp. 2651-2653, June 1989.
[20] Michel Depas, Tanya Nigam, and Marc M. Heyns “Soft Breakdown of Ultra-Thin Gate Oxide Layers” IEEE Trans. on Electron Devices, Vol. 43, No. 9, pp. 1499-1504, Sep. 1996.
[21] Andreas Martin, Paula O’Sullivan and Alan Mathewson “Dielectric Reliability Measurement Methods: A Review” Microelectron. Reliab. Vol. 38, No. 1, pp. 37-72, Aug. 1998.
[22] D. J. DiMaria and E. Cattier “Mechanism for Stress-Induced Leakage Currents in Thin Silicon Dioxide Films” J. Appl. Phys. Vol. 78, No. 6, pp. 3883-3894, Sep. 1995.
[23] Piero Olivo, Thao N. Nguyen, and Bruno Ricco, “High-Field-Induced Degradation in Ultra-Thin SiO2 Films” IEEE Trans. on Electron Devices, Vol. 35. No. 12, Dec. 1988.
[24] A. Cacciato and S. Evseev, “Independence of the Soft Breakdown Phenomenon from the Gate Material” J. Electrochem. Soc., Vol. 149, No. 10, pp. F149-F151, Sep. 2002.
[25] R. Degraeve, B. Kaczer, and G. Groeseneken, “Reliability: a Possible Showstopper for Oxide Thickness Scaling” Semicond. Sci. Technol., Vol. 15, No.5, pp.436-444, May 2000.
[26] Muhammad Ashraful Alam, Bonnie E. Weir, and Paul J. Silverman, “A Study of Soft and Hard Breakdown—Part II: Principles of Area, Thickness, and Voltage Scaling” IEEE Trans. on Electron Devices, Vol. 49, No. 2, pp.239-346, Feb. 2002.
[27] S. Bruyere, E. Vincent, and G. Ghibaudo, “Quasi-breakdown in Ultrathin SiO2 Films: Occurrence Characterization and Reliability Assessment Method” in Proc. 38th IRPS Conf., pp. 48–54, 2000.
[28] Yoshiaki Toyota, Takeo Shiba, and Makoto Ohkura, “Effects of the Timing of AC Stress on Device Degradation Produced by Trap States in Low-Temperature Polycrystalline-Silicon TFTs” IEEE Trans. on Electron Devices, Vol. 52, No. 8, pp. 1766-1771, Aug. 2005.
[29] Kueing-Long Chen, Steve Saller, and Rajiv Shah, “The Case of AC Stress in the Hot-Carrier Effect” IEEE Trans. on Electron Devices, Vol. ED-33, No. 3, pp.424-426, Mar. 1986.
[30] T Sakurai, M Kakumu, T Iizuka, “Hot-carrier Suppressed VLSI with Submicron Geometry” IEEE Int. Solid-State Circuits Conf. 85, pp.272-273, Feb. 1985.
[31] Horiuchi T., Mikoshiba H., Nakamura K., Hamano K., “Hot-Carrier Induced Degradation of n-MOSFET’s in Inverter Operation” in Proc. Symp. VLSI Technol., pp. 104-105, May 1985.
[32] Andrea Ghetti, “Gate Oxide Reliability: Physical and Computational Models” pp. 1-61, 2004.
[33] Fong, Y., Chen, I. C., Lee, J., Holland, S. and Hu, C., “Dynamic Stressing of Thin Oxides” IEDM Tech. Dig., Vol. 32, pp. 664-667, 1986.
[34] Rosenbaum E., Liu Z., and Hu C., “The Effect of Oxide Stress Waveform on MOSFET Performance” IEDM Tech. Dig., pp. 719-722, Dec. 1991.
[35] Elyse Rosenbaum, Zhihong Liu, and Chenming Hu, “Silicon Dioxide Breakdown Lifetime Enhancement Under Bipolar Bias Conditions” IEEE Trans. on Electron Devices, Vol. 40, No. 12, pp. 2287-2295, Dec. 1993
[36] J. S. Suehle and P. Chaparala, “Low Electric Field Breakdown of Thin SiO2 Films Under Static and Dynamic Stress” IEEE Trans. Electron Devices, Vol. 44, No. 5, pp. 801-808, May 1997.
[37] Bin Wang, John S. Suehle, Eric M. Vogel, and Joseph B. Bernstein, “Time-Dependent Breakdown of Ultra-Thin SiO2 Gate Dielectrics Under Pulsed Biased Stress” IEEE Electron Device Letters, Vol. 22, No. 5, pp. 224-226, May 2001.
[38] I . C. Chen, S . Holland, and C. Hu, “Oxide Breakdown Dependence on Thickness and Hole Current-Enhanced Reliability of Ultra Thin Oxides” IEDM Tech. Dig., Vol. 32, pp. 660-663, 1986.
[39] I . C. Chen, S. Holland, and C. Hu, “Electron-Trap Generation by Recombination of Electrons and Holes in SiO2” J. Appl. Phys., Vol. 61, No. 9, pp. 4544-4548, May 1987.
[40] Toshihiro Matsuda, Takashi Ohzone and Takashi Horf, “Time Dependent Dielectric Breakdown Characteristics of MOS Capacitors with Si-Implanted SiO2” Solid-State Electronics Vol. 39, No. 10, pp. 1427-1434, Jan. 1996.
[41] S. Fleischer and P. T. Lai, Y. C. Cheng, “Simplified Closed-form Trap-Assisted Tunneling Model Applied to Nitrided Oxide Dielectric Capacitors” J. Appl. Phys. Vol. 72, No. 12, pp. 5711-5715, Dec. 1992.
[42] M. Lenzlinger, E.H. Snow, “Fowler-Nordheim Tunneling into Thermally Grown SiO2” J. Appl. Phys., Vol. 40, No. 1, pp. 278-284, Jan. 1969.
[43] Z. Weinberg, “On Tunneling in Metal-Oxide-Semiconductor Structures” J. Appl. Phys., Vol. 53, pp. 5052-5056, 1982.
[44] M. Depas, B. Vermeire, P. W. Mertens, R. L. Van Merighaeghe, and M. M. Heyns, “Determination of tunneling parameters in ultra-thin oxide layer poly-Si/SiO2/Si structures” Soild-State Electron., Vol. 38, No. 8, pp. 1465-1471, 1995.
[45] Chanhyung Kim, Bongki Lee, Hee Jung Yang, Hyun Min Lee, Jae Gab Lee and Hyunjung Shin, “Effects of Surface Treatment on Work Function of ITO (Indium Tin Oxide) Films” J. Korean Phys. Soc., Vol. 47, pp. S417-S421, Nov. 2005.
[46] Y. Fong, I. C. Chen, S . Holland, J. Lee, and C. Hu, “Dynamic Stressing of Thin Oxides” IEDM Tech. Dig., Vol. 32, pp. 664-667, 1986.
[47] M. S. Liang, S. Haddad, W. Cox, and S. Cagnina, “Degradation of Very Thin Gate Oxide MOS Devices Under Dynamic High Field/Current Stress” IEDM Tech. Dig., Vol. 32, pp. 394-398, 1986.