臺灣博碩士論文加值系統

近幾年，隨著CMOS-MEMS製程的進步，微機電麥克風取代了傳統的架構成為主流，應用於不同的消費性電子產品上，如行動裝置、助聽器等。當感測器與讀出電路整合在單一晶片上時，由於微機電麥克風的電容變化量範圍約femto-Farad，所以一低雜訊的信號轉移方式於讀出電路來說顯得非常重要。

為符合低頻時低雜訊低成本的應用，本論文選擇於0.35um CMOS標準製程下設計一接面電晶體(JFET)元件當作讀出電路的輸入緩衝器使用，藉JFET特性來排除掉輸入相關雜訊的影響。為驗證JFET之可行性，多設計一MOSFET的對照組來比較。接著利用一低雜訊放大器來放大微小感測訊號，並利用高動態範圍的積分三角調變器做信號處理。模擬結果SDM部分訊號對雜訊與失真比可達70.4dB，動態範圍達102.9dB，整體讀出電路部分訊號對雜訊與失真比69.8dB，單一核心的面積為556umx381um。

In recent years, with the progress of CMOS-MEMS tech-nology, MEMS microphone gradually replaced the traditional Electret Condenser Microphone(ECM)and became the mainstream in consumer electronic products such as various mobile devices and hearing aids. When the sensor and the readout circuit are integrated together as a system-on-a-chip (SoC), because the capacitive variation of MEMS microphone is in the range of femto-Farad, a low-noise signal-translation in the readout circuit is very important.

In order to meet the requirements for low-noise, low-cost applications in the sound frequency (low frequency) range, this work uses a junction field effect transistor (JFET), which is integrated in the 0.35um CMOS standard process, as the input device for the readout circuit so as to reduce the input referred low-frequency noise. In addition, a MOSFET is in comparison with the JFET to verify the feasibility. The readout circuit includes a low-noise amplifier and a high dynamic range sigma-delta modulator (SDM) to process the signal. The simulated results of the SDM show that the peak SNDR and the dynamic range are 70.4dB and 102.9dB, respectively. The peak SNDR of the readout circuit is 69.8dB. The chip size is 556um x 381um.

誌謝......................................................i
摘要.....................................................ii
Abstract................................................iii
索引.....................................................iv
附圖索引.................................................vii
附表索引..................................................x
第一章 緒論
1-1. 研究動機..........................................- 1 -
1-2. 相關研究發展......................................- 5 -
1-3. 論文組織..........................................- 7 -
第二章 Junction FET
2-1. 接面場效電晶體操作原理.............................- 8 -
2-2. 接面場效電晶體的設計與模擬.........................- 10 -
第三章 積分三角調變器原理架構
3-1. 取樣理論與量化雜訊.............................- 14 -
3-1-1 奈奎式取樣定理...............................- 14 -
3-1-2 量化雜訊 (Quantization Noise)................- 15 -
3-1-3 超取樣定理...................................- 18 -
3-1-4 雜訊移頻(Noise shaping)......................- 19 -
3-1-5 穩定度(Stability)及線性度(Linearity)考量......- 20 -
3-2. 三角積分調變器基本架構.........................- 21 -
3-2-1 一階超取樣積分三角(Σ∆)調變器...................- 21 -
3-2-2 二階超取樣積分三角(Σ∆)調變器...................- 22 -
3-2-3 高階單迴路積分三角(Σ∆)調變器...................- 24 -
3-2-4 高階多迴路積分三角(Σ∆)調變器...................- 26 -
3-3. 結論.........................................- 27 -
第四章 積分三角調變器系統分析與行為模擬
4-1. 非理想效應.......................................- 28 -
4-1-1 熱雜訊......................................- 28 -
4-1-2 有限的運算放大器增益(Finite dc gain)..........- 30 -
4-1-3 Settling Noise..............................- 32 -
4-2. 二階積分三角調變器之行為模擬.......................- 34 -
第五章 積分三角調變器電路設計與模擬
5-1. 輸入緩衝器及低雜訊放大器...........................- 38 -
5-1-1 Input Buffer................................- 39 -
5-1-2 Operational Amplifier.......................- 40 -
5-1-3 Overall pre-ampliifier......................- 43 -
5-1-4 Two-stage Source follower buffer............- 44 -
5-2. 積分三角調變器系統架構簡介.........................- 45 -
5-2-1 交換電容式積分器(Switched-Capacitor
Integrator).................................- 45 -
5-3. 電路架構設計.....................................- 48 -
5-3-1 運算放大器...................................- 48 -
5-3-2 量化器（Quantizer）..........................- 50 -
5-3-3 非重疊時脈產生器（Non-overlapping Clock
Generator）.................................- 52 -
5-3-4 解決整合問題之Reset機制.......................- 53 -
5-3-5 輸出緩衝器(Output buffer)....................- 55 -
5-4. 讀出電路系統模擬結果..............................- 56 -
第六章 晶片佈局考量與量測結果
6-1. 晶片佈局考量.....................................- 61 -
6-1-1 JFET佈局....................................- 62 -
6-1-2 類比電路佈局.................................- 62 -
6-1-3 類比、混合訊號及數位電路的考量與配置............- 64 -
6-1-4 電源線屏蔽與穩壓..............................- 65 -
6-2. 晶片佈局圖.......................................- 66 -
6-3. PCB測試板與量測環境...............................- 68 -
6-3-1 PCB板設計與考量..............................- 68 -
6-3-2 量測環境.....................................- 70 -
6-4. 量測結果.........................................- 72 -
6-4-1 JFET元件量測結果.............................- 72 -
6-4-2 低雜訊放大器量測結果..........................- 74 -
6-4-3 積分三角調變器量測結果........................- 76 -
6-4-4 讀出電路系統量測結果..........................- 78 -
6-5. 量測結果探討.....................................- 79 -
第七章 結論與後續研究建議
7-1. 結論............................................- 87 -
7-2. 後續研究建議.....................................- 88 -
參考文獻..............................................- 90 -

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