臺灣博碩士論文加值系統

2010 年六月，IEEE P802.3ba 被正式提出，定義了40GbE 與100GbE 的規範，目的是將IEEE 802.3 的協定延伸至40Gbps 與100Gbps 的操作速度，並同時符合現行協定與傳輸距離的要求。IEEE P802.3ba 定義之100GbE 將單一通道100Gbps的光信號以波長分割多工轉換(Wavelength Division Multiplexing）分割成四條25Gbps 的子通道，以達到高速通訊傳輸的目的。
在光通信系統中，由於傳輸通道的成本相當昂貴，通常希望能在單一通道內能傳輸更高頻的資料，以減少傳輸通道的成本。在100GbE 的接收器系統，需要將四通道25Gbps 的高速信號解調至十通道10Gbps 的低速信號，此種2:5 的資料比率比起傳統2 次方倍率的解調器（e.g.,1:16 DEMUXing）設計上更為複雜，並且會有較大面積與功率消耗 ，此論文提出一1⁄2.5資料速率比的資料與時脈回復電路（Clock & Data Recovery Circuit, CDR）可以不必經過2:5 解調器便將資料分離成低頻信號，以減少硬體資源的消耗，此CDR 使用TSMC 40 奈米製程，在1-V 的電源供應下只消耗51.5mW/Channel。

In June, 2010, IEEE P802.3ba is generated officially. It defines the specification of 40GbE and 100GbE. The purpose is to extend the operation speed of the IEEE 802.3 agreement to 40Gbps and 100Gbps, and at the same time it also accords the current agreement and the demand of the transmission distance. At the definition of IEEE P802.3ba, the 100GbE is used four channels of 25Gbps output of with wavelength division multiplexing to achieve the purpose of high speed transmission.
At optical communication systems, since the cost of the transmission line channel is very expensive, in order to reduce the cost, we usually hope we can transmit higher frequency data in single channel. At the 100GbE receiver system, we need to deserialize four channel 25Gbps signal into ten channel 10Gbps. Unlike the conventional power of 2 deserializer, the 2:5 data ratio would suffer from more complicate design, and consume more area and have more power dissipation. A 1/2.5-rate clock and data recovery (CDR) circuit is proposed in this thesis. We can deserialize the signal without 2:5 deserializer to reduce the hardware resource. This CDR is implemented in TSMC 40nm CMOS technology. At 1V power supply, it only consumes 51.5mW/Channel.

摘要 i
Abstract iii
Contents v
List of Figures ix
List of Tables xiii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Conventional Receiver 3
2.1 Introduction 3
2.2 100-Gb/s Ethernet 4
2.2.1 Introduction 4
2.2.2 Architecture 5
2.2.3 Physical Coding Sublayer (PCS) 6
2.2.4 Physical Medium Attachment (PMA) 7
2.2.5 Physical Media Dependent (PMD) 9
2.3 Receiver 11
2.3.1 Limiting Amplifier 11
2.3.2 Clock and Data Recovery Circuit 12
2.3.3 Deserializer 13
2.4 The Prior Arts 15
2.4.1 100 Gb/s Ethernet Chipsets in 65nm CMOS Technology 15

2.4.2 A 10:4 MUX and 4:10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link 16
Chapter 3 A 1/2.5-Rate Clock and Data Recovery Circuit for 100 Gb/s Ethernet in 40nm Technology 19
3.1 Introduction 19
3.2 Proposed 1/2.5-Rate Clock and Data Recovery Circuit 20
3.3 Power Consumption Analysis 23
3.4 Phase and Frequency Mismatch in Delay Line 29
3.5 Summary 36
Chapter 4 Circuit Implementation of 1/2.5-Rate CDR 41
4.1 Introduction 41
4.2 Building Block 41
4.2.1 1/2.5-Rate Phase Detector 41
4.2.2 Delay-Locked Loop 46
4.2.3 Phase Interpolator 53
4.2.4 Data retimer 56
4.3 Simulation Results 57
4.3.1 1/2.5-Rate Phase Detector 57
4.3.2 1/2.5-Rate CDR 59
4.4 Summary 61
Chapter 5 Experimental Results 63
5.1 Introduction 63
5.2 Chip Die Photo 63
5.3 Measurement Setup 64
5.4 Measurement Results 64
5.5 Summary 68
Chapter 6 Conclusions and Future Works 69
6.1 Conclusions 69
6.2 Future Works 69
Bibliography 71

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