臺灣博碩士論文加值系統

隨著科技的進步，電視廣播也隨之進入數位化系統，通道編解碼身為其重要的一環，自然值得我們來探討研究。在眾多通道編解碼裡面，由歐盟所提出的地面數位影像廣播系統中使用理德索羅門碼與維特比解碼，本文將目標放在理德所羅門解碼器的討論。文中我們將對柏林坎-馬西ㄧ些以面積考量的理德所羅門解碼器做比較，採用最佳的模式。另一方面，改良有限場乘法器架構，在運作速度的考量下，減少乘法器所需要的邏輯閘數。藉此兩種方法使里德所羅門解碼器節省面積後速度達最佳化。最終，以硬體描述語言設計，解碼器共花費2228 Logic Elements和5400 Memory Bits，以邏輯分析儀來檢測APEX20K硬體的輸出，驗證無誤。

With the advances of science and technology, television broadcasting also moves into the digital era. Therefore, channel coding-decoding is worthy of conferring and researching because it is important for digital television broadcasting systems. The DVB-T published by European Broadcast Union makes use of Reed-Solomon code and viterbi decoder for channel codec. In this thesis we, first at all, compare some Reed-Solomon decoders that take account of area and find the best algorithm of them in this system. Thereafter we reform a structure of finite field multiplier which reducing the amount of logic gate without losing operation speed to optimize the speed of a Reed-Solomon decoder after reducing area. By the two ways, this decoder is designed with VHDL and verified through APEX20K Demo Board by Logic Analyzer. It occupies 2228 logic elements and 5400 memory bits.

誌謝……………………………………………………I
摘要……………………………………………………II
Abstract……………………………………………………III
目錄………………………………………………………IV
圖目錄………………………………………………… V
表目錄……………………………………………………VII
第一章 緒論…………………………………………1
1.1數位電視廣播簡介……………………………………2
1.2 DVB-T系統簡介………………………………………3
第二章　理德所羅門碼原理……………………………5
2.1有限場(伽羅瓦場) GF(2m)…………………………5
2.2 理德所羅門碼介紹…………………………………6
2.3 Reed-Solomon編碼………………………………7
2.4 Reed-Solomon解碼演算法…………………………8
2.4.1 Berlekamp-Massey Algorithm (BM演算法)……11
2.4.2 Chien Search……………………………………14
2.4.3 Forney演算法……………………………………14
第三章 硬體架構設計………………………………16
3.1 有限場乘法器………………………………………16
3.2 Reed-Solomon編碼器………………………………20
3.3 Reed-Solomon解碼器架構…………………………22
3.3.1 錯誤徵狀的計算(Syndrome Calculator)………22
3.3.2 Berlekamp-Massey Algorithm…………………24
3.3.3 Chien Search & Forney演算法…………………29
第四章　實作與模擬驗證………………………………31
4.1 系統設計流程………………………………………31
4.2 軟體模擬……………………………………………32
4.3 理德所羅門電路……………………………………35
4.4 硬體實現驗證………………………………………38
4.5 性能分析……………………………………………41
4.6 晶片佈局……………………………………………43
第五章　結論……………………………………………44
參考文獻…………………………………………………45

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