臺灣博碩士論文加值系統

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With the advances in integrated circuit(IC) process, IC design issues that need to be handled will be more difficult. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce the cost of IC design and manufacturing, structured ASIC emerges as a new design alternative. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A base block for structured ASICs must provide powerful functional expression, high integration density, and flexibility to meet various application requirements. Moreover, it should also minimize the efforts of developing tools for chip designs. We propose three implementations of 3-LUT, two are the from previous work and one is newly invented. Experimental results show that the well-known three-input lookup table (3-LUT) implemented with multiplexers achieves best timing performance, smallest area, and low power dissipation than others implementations.

ABSTRACT iv
Contents vi
List of Figures viii
List of Tables x
Chapter 1. Introduction 1
1.1.Background 1
1.2. Scope of the Work and Contributions 2
1.3. Thesis Organization 4
Chapter 2. Related Work 5
2.1. Existing VCLBs 5
2.2. VCLB for Structured ASIC 6
2.3. Via Patterned Gate Array (VPGA) 9
2.4. 4-LUTs for Structured ASIC 10
2.5. S3 Structure 11
2.6. Modified S3 Structure 12
Chapter 3. Proposed LUTs 14
3.1. Mux L3 14
3.1.1 Via Configurations 18
3.1.2 Combinational Cells 19
3.1.3 Sequential Cells 21
3.1.4 Mux L3M 22
3.2. Dual-ND L3 25
Chapter 4. Design Methodology 27
4.1 FlowMap Flow 28
4.2 Synopsys Design Compiler Flow 29
4.3 Delay Envelope 29
Chapter 5. Experimental Results 31
Chapter 6. Conclusions and Future Work 41
References 42

[1]Zvi Or-bach, “Paradigm Shift in ASIC Technology In-stand Metal Out-stand Cell,” http://www.easic.com.
[2]Behrooz Zahiri, “Structured ASICs: Opportunities and Challenges,” ICCD, pp. 404-409, 2003.
[3]J. Cong and Y. Ding, "FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Trans. on CAD, Vol. 13, No. 1, Jan. 1994, pp. 1-12.
[4]N. Jayakumar and S. P. Khatri, “A Metal and Via Maskset Programmable VLSI Design Methodology using PLAs,” ICCD, 2004, pp. 590–594.
[5]B. Hu, H. Jiang, Q. Liu, and M. Marek-Sadowska, “Synthesis and Placement Flow for Gain-Based Programmable Regular Fabrics,” ISPD, 2003, pp. 197–203.
[6]C. Patel, A. Cozzie, H. Schmit, and L. Pileggi, “An architectural exploration of via patterned gate arrays,” ISPD, 2003, pp. 184–189.
[7]N. V. Shenoy, J. Kawa, R. Camposano, “Design Automation for Mask Programmable Fabrics,” DAC, 2004, pp. 192-197.
[8]Y. Ran and M. Marek-Sadowska, "Designing via-configurable logic blocks for regular fabric", IEEE Trans. on VLSI Systems, Vol. 14, No. 1, Jan. 2006.
[9]L. Pileggi, et al., “Exploring regular fabrics to optimize the performance-cost trade-off,” DAC, 2004, 782-787.
[10]Mei-Chen Li, “Standard Cell Like Via-Configurable Logic Block for Structured ASICs” M. Eng. Thesis, Yuan Ze University, Taiwan, R.O.C. July 2007.
[11]V. Betz and J. Rose, “VPR: A new packing, placement and routing tool for FPGA research,” International Workshop on Field Programmable Logic and Applications, pp. 213-222, 1997.
[12]Hou-Yu Pang, “Standard Cell Like Via-Configurable Look-Up-Table Design for Structured ASICs” M. Eng. Thesis, Yuan Ze University, Taiwan, R.O.C. July 2008.
[13]A. Koorapaty, L. Pileggi, and H. Schmit, “Heterogeneous logic block architectures for via-patterned programmable fabrics,” LNCS 2778, 2003, pp. 426–436.
[14]A. Koorapaty, V. Kheterpal, P. Gopalakrishnan, M. Fu, and L. Pileggi “Exploring logic block granularity for regular fabrics,” DATE, 2004, pp. 1468-473.
[15]M. C. Li, H. H. Tung, C. C. Lai, and R. B. Lin, “Standard cell like via-configurable logic block for structured ASICs,” ISVLSI 2008, pp.381-386.
[16]K. C. Wu and Y. W. Tsai, “structured ASIC, evolution or revolution?” ISPD, pp.103-106, 2004.
[17]HardCopy Structured ASICs: ASIC gain without the pain. http://www.altera. com/products/software/flows/asic/qts-structured_asic.html
[18]White paper, “RapidChip technology: fast custom silicon through platform-based design,” LSI Logic, 2004.
[19]T. Okamoto, T. Kimoto, and N. Maeda, “Design methodology and tools for NEC electronics’ structured ASIC ISSP,” ISPD, 2004, pp.90-96.
[20]“EDA Survey Results,” Deutsche Bank Securities, June 23, 2005.
[21]B. Zahiri, “Structured ASICs: opportunities and challenges,” ICCD, 2003, pp. 404-409.
[22]Y. Ran and M. Marek-Sadowska, “Via-configurable routing architectures and fast design mappability estimation for regular fabrics,” IEEE Trans. on VLSI Systems, Vol. 14, Sept. 2006, pp. 998-1009.
[23]F. Mo, and R. Brayton, “PLA-based regular structures and their synthesis,” IEEE Trans. on TCAD, Vol. 22, No. 6, June 2003, pp.723 - 729.
[24]N. Jayakumar and S. P. Khatri, “A metal and via maskset programmable VLSI design methodology using PLAs,” ICCD, 2004, pp. 590-594.
[25]N. V. Shenoy, J. Kawa, and R. Camposano, “Design automation for mask programmable fabrics,” DAC, 2004, pp. 192-197.
[26]D. D. Sherlekar, “Design considerations for regular fabrics,” ISPD, April 18-21,2004, pp.97-102.
[27]V. Kheterpal, et al., “Design methodology for IC manufacturability based on regular logic-bricks,” DAC, 2005, pp.192-197.
[28]A. Nakamura, M. Kawarasaki, K. Ishibashi, M. Yoshikawa, and T. Fujino, “Regular fabric of via programmable logic device using exclusive-or array (VPEX) for EB direct writing,” IEIEC Trans. Electron., Vol. E91-C, No. 4, pp. 509-516, April 2008.
[29]M. Pons, F. Moll, A. Rubio, J. Abella, X. Vera, and A. Gonz?lez, “Via-configurable transistor array: a regular design technique to improve ICs yield,” IEEE Intl. Workshop on Design for Manufacturability and Yield, 2007.
[30]S. Gopalani, R. Garg, S. P. Khatri, and M. Cheng, “A lithography-friendly structured ASIC design approach,” GLSVLSI, 2008, pp. 315-320.
[31]K. Gulati, N. Jayakumar, and S. P. Khatri, “A structured ASIC design approach using pass transistor Logic,” ISCAS, May 2007, pp. 1787-1790.
[32]N. Weste and D. Harris, CMOS VLSI Design, Third Edition, Addison Wesley, Boston, 2005.