臺灣博碩士論文加值系統

本論文提出考慮邊緣電容對於窄通道完全解離絕緣體上矽N型金氧半元件的閘-源/汲極及源/汲-閘極電容行為之分析。

第一章主要是對SOI元件做簡介，介紹SOI元件的特性以及本論文中所探討的孤島式隔離SOI元件結構，此外我們並說明了邊緣電場效應對於小尺寸SOI元件之影響。

第二章則是比較不同通道寬度的SOI元件受到邊緣電容效應時對總電容的影響，我們也算出邊緣電容對總電容的百分比貢獻，重要的是，我們藉由模擬出邊緣電容和通道寬度的關係來了解窄通道元件在不同通道寬度時邊緣電容的變化。

第三章比較當孤島式隔離SOI元件使用或不使用輕摻雜汲極時，對元件的直流特性分析及邊緣電容對閘-源/汲極電容行為之影響。

This thesis reports the analysis of the Gate-Source/Drain
and Source/Drain-Gate capacitance behavior of narrow channel FD SOI NMOS Device considering the fringing capacitance.


The first chapter introduces the characteristic of the SOI Device and the Mesa Isolation SOI Device. Moreover, we also account for the impact of Fringing Electric Field Effect on the Small- Geometry SOI Device.


The second chapter compares the impact on the total capacitance behavior of different channel width SOI Device due to the Fringing Capacitance Effect .we also compute out the percentage contribution of the fringing capacitance on the total capacitance. Above all, we simulate out the relationship of fringing capacitance and channel width to understand the accidence of the fringing capacitance on the different channel width.


The third chapter compares the Mesa Isolation SOI Device which uses or not uses Lightly-Doped-Drain on the analysis of DC characteristic and the Gate-Source/Drain capacitance behavior affected by the fringing capacitance.

第1章 導論…………………………………………………1
1.1 SOI元件的簡介…………………………………………1
1.2 SOI元件縮小時產生的問題……………………………3
1.3 孤島式隔離SOI元件結構的特性………………………4
1.4 SOI元件的邊緣電場及邊緣電容效應…………………5
1.5 本篇論文的目標 ………………………………………6

第2章 窄通道元件因邊緣電場效應對於邊緣電容行
為之影響……………………………………………7
2.1 簡介……………………………………………………7
2.2 CGS及CGD模擬結果……………………………………8
2.2.1 邊緣電容佔總電容之百分比………………………18
2.2.2 邊緣電容和通道寬度之關係………………………21
2.2.3 討論…………………………………………………24
2.3 CSG及CDG模擬結果……………………………………28
2.4 結論……………………………………………………33

第3章 考慮邊緣電容效應對於有輕摻雜汲極之完全解離絕緣體
上矽N型金氧半元件電容行為之影響……………34
3.1 簡介……………………………………………………34
3.2 直流模擬結果…………………………………………36
3.3 交流模擬結果…………………………………………41
3.3.1 CGS及CGD模擬結果…………………………………41
3.3.2 邊緣電容佔總電容之百分比………………………46
3.3.3 CSG及CDG模擬結果…………………………………48
3.4 結論……………………………………………………51

第4章 總結…………………………………………………53

參考文獻 ……………………………………………………54

第1章…………………………………………………………54
第2章…………………………………………………………55
第3章…………………………………………………………56

第１章

[1.1]J. B. Kuo and S. C. Lin, ”Low-Voltage SOI CMOS Devices and Circuits,” Wiley Interscience,New York, 2001.

[1.2]SURYA VEERARAGHAVAN and JERRY.FOSSUM, ”Short-Channel Effects in SOI MOSFET’s.”IEEE Trans. Electron Devices, Vol. 36, No 3. pp. 522- 528,March,1989.

[1.3]H. Wang, M. Chan, Y. Wang, and P. K. Ko, ”The Behavior of Narrow -Width MOSFET’s with MESA Isolation,” IEEE Trans. Electron Devic -es, Vol. 47, No. 3, pp. 593-600,March, 2000.

[1.4]Guruprasad Katti, Nandita DasGupta, and Amitava DasGupta, ”Thre -shold Voltage Model for Mesa-Isolated Small Geometry Fully Depleted SOI MOSFETs Based on Analytical Solution of 3-D Poisson’s Equati –on.”IEEE Trans On Electron Devices, vol .51, No. 7,pp. 1169-1177,July, 2004.

[1.5]J. B. Kuo, Y. G. Chen and K. W. Su, ”Sidewall-Related Narrow Channel Effect in Mesa-Isolated Fully-Depleted Ultra-Thin SOI NMOS Devices.”IEEE Electron Device Letters, Vol. 16, No. 9, pp. 379-381, Sept, 1995.

[1.6]Chun-Yen Chang,Sun-Jay Chang,Tien-Sheng Chao,Sung-Dtr Wu,andTiao-Yuan Huang,”Reduced Reverse Narrow Channel Effect in Thin SOI nMOSFETs,” IEEE Electron Devices Letters,vol.21,No.9,pp. 460- 462, September , 2000.

[1.7]J. Pretet ,T. Emst, S .Cristoloveanu ,C.Raynaud,”Narrow-Channel Effects in LOCOS-Isolated SOI MOSFET with Variable Thickness,”IEEE SOI International Conference ,pp. 66-67 Oct ,2000.

[1.8]Nihar . R. Mohapatra, A. Dutta, M. P. Desai,”Effect of Fringing Capacitances in Sub 100nm MOSFET’s with High-K Gate Dielectrics,”IEEE, pp. 479- 482, 2000.

[1.9]Aditya Bansal,Bipul C. Paul,and Kaushik Roy,”Modeling and Optimi zation of Fringe Capacitance of Nanoscale DGMOS Devices,” IEEE Trans Electron Devices, Vol. 52, No. 2,pp. 256-262, February 2005.

[1.10]Yu-Sheng Lin,”Fringing Induced Charge Effect (FICE) on Capacitance Behavior of 100nm FD SOI NMOS Device with HfO2 Gate Dielectric,”pp. 19-34,June, 2005.


第2章

[2.1]J. B. Kuo and S. C. Lin, ”Low-Voltage SOI CMOS Devices and Circuits,” Wiley Interscience,New York, 2001.

[2.2]J. B. Kuo, Y. G. Chen and K. W. Su, ”Sidewall-Related Narrow Channel Effect in Mesa-Isolated Fully-Depleted Ultra-Thin SOI NMOS Devices,” IEEE Electron Device Letters, Vol. 16, No. 9, pp. 379-381, Sept, 1995.

[2.3]H. Wang, M. Chan, Y. Wang, and P. K. Ko, ”The Behavior of Narrow -Width MOSFET’s with MESA Isolation,” IEEE Trans. Electron Devices, Vol. 47, No. 3, pp. 593-600, March, 2000.

[2.4]K. W. Su and J. B. Kuo, ”Analytical Threshold Voltage Formula Including Narrow Channel Effects for VLSI Mesa-Isolated FD Ultrathin SOI NMOS Devices,” Japanese J. Applied Physics, pp. 4010-4019, Aug. 1995.

[2.5]K. W. Su and J. B. Kuo, ”Compact Current Model for Mesa-Isolated FD SOI NMOS Devices Considering Sidewall-Related Narrow Channel Effects,” IEEE SOI Conf. Digest, pp. 84-85, 1997.

[2.6]G. Katti, N. DasGupta, and A. DasGupta, ”Threshold Voltage Model for Mesa-Isolated Small Geometry Fully Depleted SOI MOSFETs Based on Analytical Solution of 3-D Poisson’s Equation,” IEEE Trans. Electron Devices, Vol. 51, No. 7, pp. 1169-1177, July, 2004.

[2.7]K. Kumagai, H. Iwaki, A. Yoshino and S. Kurosawa, ”A 3D Analysis of Source/Drain Capacitance in SOI MOSFET for Practical Circuit Design,” IEEE SOI Conf. Proc. pp. 15-16, Oct. 1994.

[2.8]Davinci, Three-Dimensional Device Simulator Program, Technology Modeling Associates, Inc, 1996.

[2.9]P. Yang and P. K. Chatterjee, ”SPICE Modeling for Small Geometry MOSFET Circuits,”IEEE Trans. CAD of IC and Systems, Vol. CAD-1, No. 4, pp. 169-182, Oct.1982.


第3章

[3.1]Y. Pan, K. K. Ng, and C. C. Wei,”Hot-Carrier Induced Electron Mobility and Series Resistance Degradation in LDD NMOSFET’s,”IEEE Electron Devices Letters, Vol. 15, No. 12.pp. 499-501,December 1994.

[3.2]Ru Huang, Jinyan Wang, Xing Zhang, IEEE, and Yangyuan Wang,”Hot Carrier Induced Degradation in Mesa-Isolated n-Channel SOI MOSFETs Operating in a Bi-MOS Mode,”IEEE Trans Electron Devices, Vol. 48,No. 8, pp. 1594-1597,August, 2001.

[3.3]Tomohisa Mizuno, akashi Kobori, Yoshikazu Saitoh, Shizuo Sawada, and Takeshi Tanaka,”Gate-Fringing Field Effects on High Performance in High Dielectric LDD Spacer MOSFET’s,”IEEE Trans Electron Devices. Vol. 39. No. 4. pp. 982-988,April, 1992.

[3.4]Jyh-Chyurn Guo, Chih-Yuan Lu, Charles Ching-Hsiang Hsu,Pole-Shang Lh,and Steve Shao-ShiunChung,”Performance and Reliability Evaluation of High Dielectric LDD Spacer on Deep Sub-Micrometer LDD MOSFET,” IEEE Trans Electron Devices, Vol. 41, No. 7, pp. 1239-1247, July, 1994.

[3.5]Man-Chun Hu, Sheng-Lyang JANG and Chwan-Gwo CHYAU,”A Physics-Based Short-Channel Current-Voltage Model for Lightly -Doped-Drain Metal-Oxide-Semiconductor Field-Effect-Transistors,”
,Jpn. J. Appl. Phys. Vol. 36(1997) pp. 3448-3459 Part 1,No. 6A,June , 1997.

[3.6]S.C.Lin and J.B.Kuo,”Fringing-Induced Barrier Lowering(FIBL) Effects of 100nm FD SOI NMOS Devices with High Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer,” 2002 IEEE International SOI Conference, pp. 93-94.

[3.7]James B. Kuo and Shih-Chia Lin,”The Fringing Electric Field Effect on the Short-Channel Effect Threshold Voltage of FD SOI NMOS Devices with LDD/Sidewall Oxide Spacer Structure,” IEEE, pp. 1-4, 2002.

[3.8]S. C. Lin and J. B. Kuo,”Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI nMOS Devices With the LDD/Si dewall- Oxide Spacer Structure,” IEEE Trans Electron Devices,Vol. 50, No. 12, pp. 2559-2563,December, 2003.

[3.9]M.Inuishi,K. Mitsui, S. Kusuniki, H. Oda, K.Tsukamoto and Y. Akas-aka,”GATE CAPACITANCE CHARACTERISTICS OF GATE /N- OVER-LAP LDD TRANSISTOR WITH HIGH PERFORMANCE AND HIGH RELLIABILITY,”IEEE,IEDM, pp. 91-371~374,1991.

[3.10]P. Klein, K. Hoffmann, B. Lemaitre,”Description of the Bias Depe -ndent Overlap Capacitance at LDD MOSFETs for Circuit Applications,”IEEE,IEDM, pp. 93- 493~496,1993.