臺灣博碩士論文加值系統

針對多樣且日益複雜的嵌入式系統應用，近年來興起的多核心架構平台（Multi-Core Platform），已被視為能以合理的成本滿足高運算需求的方案之一。其中以一微處理器單元（MPU）搭配一數位訊號處理器（DSP）的異質性雙核心處理器平台（Heterogeneous Dual-Core Platform），是目前行動多媒體嵌入式系統的主流。在異質雙核心處理器平台中，微處理器單元將具有高運算需求的工作（Task），交由數位訊號處理器作加速，藉此可達到有效率的分工並降低系統的耗能; 然而，繁複且不具效率的工作管理（Task Management），包括工作排程（Task Schedule）、工作指派（Task Dispatch）等，會因為處理器間的互動與複雜的處理器間的溝通（Inter-Processor Communication, IPC），造成異質性雙核心處理器平台的效能大為降低。為提升數位訊號處理器的效能，本論文提出一適用於多媒體應用之多執行緒數位訊號協同處理器，該協同處理器包括一負責與微處理器單元溝通、協調之精巧協同處理器介面（Smart Coprocessor Interface, SCI），以及具零管線延遲（Zero Pipeline Latency）特性之交錯式多執行緒（Interleaved Multithreaded）數位訊號處理器。所提之精巧協同處理器界面，可動態管理工作分派，並可有效的解決處理器間的溝通問題。為評估精巧協同處理器界面對數位訊號處理器效能的影響，本論文利用CoWare電子系統層級（ESL）設計方法，建構一雙核心處理器虛擬平台（Virtual Platform）。以一張256x256 JPEG壓縮為例，所提之精巧協同處理器界面，分別較傳統以微處理器單元透過作業系統（如Linux）、或在數位訊號處理器上執行微核心（Micro-Kernel或 RTOS）進行兩處理器間的工作管理，減少約68% 以及15 %的執行時間。另一方面，所提之數位訊號處理器的資料路徑為一加法器（A）、一乘法器（M）、一累加器（A）、與一移位器（S）的串接（Cascade）組合。此AMAS複雜資料路徑（Composite Datapath）可執行加乘(AM), 乘加(MA), 加-乘-累加-位移(AMAS)等多媒體應用常見的運算。最後，我們利用TSMC 0.13μm CMOS 製程，實做所提出之數位訊號協同處理器，其操作頻率為250MHz，平均消耗40mW功率。該晶片面積為2.7 x 2.7 mm2，而精巧協同處理器界面僅佔約0.65%的晶片面積。

Due to task divergence in most embedded systems, heterogeneous dual-core/multi-core SoC, i.e. RISC+DSP, is accepted as a cost-effective solution for the increasing computation demands in mobile media applications. TI Davinci, for example, is one popular dual-core platform, where the DSP, as the slave or coprocessor, performs the computation-intensive task sent and requested by the host processor (i.e. RISC). However, inefficient DSP-task management, such as task scheduling and task dispatch, induces inter-processor communication (IPC) overheads and thus lowers the DSP performance. In order to improve DSP performance, a multithreaded DSP coprocessor for multimedia applications is proposed in this thesis. The DSP coprocessor consists of a smart coprocessor interface (SCI) and an application-specific interleaved multithreaded datapath. The proposed SCI can dynamically manage DSP-tasks and effectively reduce IPC overheads, while the interleaved multithreaded datapath can exploit thread-level parallelism (TLP) to tolerate full pipeline latency. A dual-core SystemC transaction-level virtual platform, constructed by CoWare electronic system level (ESL) design platform, is used to evaluate the DSP performance affected by the SCI. To encode a 256x256 JPEG image, the SCI reduces 68% and 15% total execution time comparing that with task management on MPU supported by OS and on DSP supported by a μ-kernel or RTOS, respectively. On the other hand, a cascaded adder, multiplier, accumulator, and shifter (A-M-A-S) functional units are applied on the proposed DSP datapath. This composite datapath is able to perform complicated operations, such as addition-multiplication (AM), multiplication-accumulation (MA), and addition-multiplication-accumulation-shift (AMAS) for multimedia applications. The proposed multithreaded DSP coprocessor is implemented by TSMC 0.13μm CMOS technology. The implementation results show that it can operate at 250MHz with 40mW power consumption. The chip area is 2.7x 2.7mm2 and the SCI occupies only 0.65% of the total chip size

1 INTRODUCTION 1
1.1 INTER-PROCESSOR COMMUNICATION (IPC) OVERHEAD 2
1.2 PIPELINE LATENCY 4
1.3 THESIS ORGANIZATION 7
2 DUAL-CORE SOFTWARE ARCHITECTURE 9
2.1 TASK MANAGEMENT ON MPU 9
2.2 TASK MANAGEMENT ON DSP 12
3 SMART COPROCESSOR INTERFACE 15
3.1 TASK MANAGEMENT 16
3.1.1 Data Structure for Task Management 19
3.1.2 Task Scheduling Policy 21
3.1.3 Task Loading Mechanism 23
3.2 MEMORY MANAGEMENT 26
3.3 INTER-PROCESSOR COMMUNICATION 29
4 MULTITHREADED DATAPATH 33
4.1 MULTITHREADED ARCHITECTURES 33
4.2 COMPOSITE DATAPATH 38
5 EXPERIMENT & IMPLEMENTATION RESULTS 43
5.1 SIMULATION PLATFORM 43
5.2 SIMULATION SCENARIO 45
5.3 SIMULATION & ESTIMATION RESULTS 46
5.4 IMPLEMENTATION RESULTS 50
5.4.1 Microarchitecture of Proposed SCI 53
5.4.2 Microarchitecture of the Proposed DSP Coprocessor 56
5.4.3 Silicon Implementation 61
6 CONCLUSION AND FUTURE WORKS 63

[1] DaVinci Technology Background and Specification, Texas Instruments, Jan. 2007. Available online: http://focus.ti.com/lit/an/sprt401a/sprt401a.pdf
[2] OMAP Platform Processors, Software and Support, Texas Instruments. Available online: http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&navigationId=11988&contentId=4638
[3] DSPLinux, http://www.cadenux.com/ridgerun
[4] SangBae Lee, "Analysis of interrupt entry latency in Linux 2.4 vs 2.6", presented at CELF Embedded Linux Conference, 2007
[5] Shih-Hao Ou, Tay-Jyi Lin, et al., "Multithreaded coprocessor interface for multi-core multimedia SoC," ASPDAC, Seoul, January 2008
[6] Linux DSP Gateway Specification, rev. 3.3.1, Nokia, Sep. 2006. Available online: http://dspgateway.sourceforge.net/pub/3.3.1/DSP_Gateway331_spec_a.pdf
[7] DSP/BIOS Timing Benchmarks for Code Composer Studio v2.2. Application Report SPRA900B, Texas Instruments, Inc., April, 2004.
[8] J. L. Hennessy and D. A. Patterson, Computer Architecture – Quantitative Approach, 3rd Edition, Morgan Kaufmann, 2002
[9] TMS320 DSP/BIOS User Guide, Texas Instruments, Inc., Nov, 2001.
[10] E. A. Lee and T. M. Pards, “Dataflow process networks,” in Proc. IEEE, vol83, 1995.
[11] Gregory T. Byrd and Mark A. Holliday, “Multithread processor architectures,” IEEE Sp, August 1995, pp. 38-46.
[12] Theo Ungerer, Borut Robic, and Jurij ilc, “A survey of Processors with explicit multithreading,” ACM Computing Surveys, 2003.
[13] J. S. Kowalik, on Parallel MIMD Computation: HEP Supercomputer and Its Applications, MIT Press, Cambridge, 1985, pp. 41–55.
[14] ALVERSON R., CALLAHAN D., and CUMMINGS D. et al., "The Tera computer system". Proceedings of the 4th International Conference on Supercomputing, 1990, pp. 1-6.
[15] Poonacha Kongetira, Kathirgamar Aingaran, and Kunle Olukotun,"Niagara: A 32-Way Multithreaded Sparc Processor", IEEE Micro, v.25 n.2, 2005, pp. 21-29.
[16] AGARWAL A., KUBIATOWICZ J., and KRANZ D. et al.,"Sparcle: an evolutionary processor design for large-scale multiprocessors". IEEE Micro 13, 3, 1993, pp. 48–61.
[17] MIKSCHL A. and DAMM W. "Msparc: a multithreaded Sparc", Lecture Notes in Computer Science, vol. 1123, 1996, pp. 461–469.
[18] Yaniv Pessach,"Make It Snappy: Juice Up Your App with the Power of Hyper-Threading", MSDN Magazine, June 2005.
[19] Gero Dittmann,“Organizing pattern libraries for ASIP design", IBM Research Report RZ3488, 2003.
[20] K. K. Parhi, VLSI Digital Signal Processing Systems – Design and Implementation, John Wiley & Sons, 1999.
[21] CoWare, Inc. http://www.coware.com
[22] μC/OS-II, http://www.micrium.com/products/rtos/kernel/rtos.html
[23] Valentine, B. Sohm, O. "Optimizing the JPEG2000 binary arithmetic encoder for VLIW architectures " ICASSP, May 2004
[24] B. Flachs et al., “The Microarchitecture of the Synergistic Processing Unit of Cell Architecture Processor”, ISSCC 2005, pp. 134-135
[25] Hao-I Yang, Ming-Hung Chang, et al,. “A Low-Power Low-Swing Single-Ended Multi-Port SRAM”, VLSI DAT 2007.
[26] M. Wroblewski, M. Mueller, A. Wortmann, S. Simon, W. Pieper, and J. A. Nossek, “A power efficient register file architecture using master latch sharing,” in Proc. ISCAS, May 2003
[27] McNutt G., and Fischer T., “Using Linux to Control DSP Processor in Mixed-Processor Systems”, Embedded Edge, Issue 4, pp 8-13, October, 2001.