臺灣博碩士論文加值系統

本論文提出了一個在 0.18um 製程、工作電壓為 1.8V 、週期為 3ns 架構下之可分辨量化電源雜訊之自行檢驗偵測電路。當電源產生電壓雜訊產生時，本論文電路可自行偵測電源雜訊訊號，且透過源極隨耦器將電壓雜訊偵測範圍由原先僅能偵測大於 30% VDD 之電壓雜訊，提升至可偵測大於 10% VDD 之電壓雜訊。本電路並結合可分辨量化電壓雜訊大小並分類計數之功能，此電路將電源雜訊分為五類，各類別電壓雜訊偵測成功率皆大於 95% 以上。

In this thesis, we proposed a self-checking power supply noise detector and analyzer in TSMC 0.18um technology, with 1.8V supply voltage and 3ns clock duration. By applying source follower, the noise detection range can be enhanced from 30% VDD to 10% VDD in our proposed power supply noise detector. Moreover, in the proposed power supply noise analyzer circuit not only can distinguish the size of power supply noise but also can sort and count the occurrence number of power supply noise. The detected noise can be classified into five levels. The detection accuracy in each level can be higher than 95%.

目錄

指導教授推薦書…………………………………………………………
口試委員會審定書………………………………………………………
著作授權書………………………………………………………… iii
誌謝………………………………………………………………… iv
中文摘要…………………………………………………………… v
英文摘要…………………………………………………………… vi
目錄………………………………………………………………… vii
圖目錄……………………………………………………………… ix
表目錄……………………………………………………………… xi
第一章 研究背景簡介……………………………………………… 1
1.1 研究背景……………………………………………………… 1
1.2 研究動機……………………………………………………… 2
1.3 研究摘要……………………………………………………… 3
1.4 研究結構……………………………………………………… 4
第二章現有雜訊檢驗偵測技術簡介……………………………… 6
2.1 自行檢驗偵測技術…………………………………………… 6
2.2 內建式探測電路……………………………………………… 8
2.3 雜訊監測電路………………………………………………… 11
2.4 峰值偵測電路………………………………………………… 15
2.5 現有雜訊檢驗偵測技術之改良與利用…………………… 18
第三章 可分辨量化電源雜訊之自行檢驗偵測電路設計……… 21
3.1 雜訊偵測輸入端…………………………………………… 23
3.2 雜訊偵測輸出端…………………………………………… 25
3.3 二進位非同步計數器……………………………………… 28
3.4 分辨雜訊大小……………………………………………… 30
3.5 同步控制器………………………………………………… 31
3.6 計數雜訊發生次數………………………………………… 33
第四章 電壓雜訊偵測能力比較………………………………… 36
4.1 電路規格比較……………………………………………… 36
4.2 偵測能力規格比較………………………………………… 37
4.3 電路佈局模擬比較………………………………………… 39
第五章 結論與未來研究方向…………………………………… 55
5.1 結論………………………………………………………… 55
5.2 未來研究方向……………………………………………… 56
參考文獻…………………………………………………………… 58



圖目錄

圖 2-1. 自行檢驗偵測電壓雜訊電路架構圖……………………… 7
圖 2-2. 自行檢驗偵測電壓雜訊電路波形………………………… 8
圖 2-3. 內建式探測電路架構圖…………………………………… 9
圖 2-4. 內建式探測電路測試波形……………………………… 10
圖 2-5. 內建式探測電路測試結果……………………………… 11
圖 2-6. 雜訊監測電路…………………………………………… 12
圖 2-7. 雜訊監測動作原理……………………………………… 13
圖 2-8. 雜訊監測電路測試波形………………………………… 14
圖 2-9. 雜訊監測電路測試結果………………………………… 14
圖 2-10. 峰值偵測電路架構圖…………………………………… 16
圖 2-11. 峰值偵測電路圖………………………………………… 16
圖 2-12. 峰值偵測電路時序圖…………………………………… 17
圖 3-1. 可分辨量化電壓雜訊之自行檢驗偵測電路圖………… 22
圖 3-2. 改良式自行檢驗偵測電壓雜訊電路方塊圖…………… 22
圖 3-3. 改良式自行檢驗偵測電壓雜訊電路輸入架構………… 23
圖 3-4. 電壓雜訊經過 SF 使其偏壓至一適當位準 VDD`…… 24
圖 3-5. 本篇論文與原始電路偵測電壓雜訊範圍測試………… 25
圖 3-6. 無重置訊號之自行檢驗偵測電壓雜訊電路輸出……… 26
圖 3-7. 改良式自行檢驗偵測電壓雜訊電路輸出架構圖……… 27
圖 3-8. 改良式自行檢驗偵測電壓雜訊電路輸出測試結果…… 28
圖 3-9. 12 位元二進位非同步計數器電路示意圖……………… 29
圖 3-10. 二進位非同步計數器計數電壓雜訊發生次數結果…… 29
圖 3-11. 分辨量化電壓雜訊大小並分類計數電路架構圖……… 30
圖 3-12. 無同步電路之計數結果………………………………… 31
圖 3-13. 同步控制器電路圖……………………………………… 32
圖 3-14. 同步控制器電路測試結果……………………………… 33
圖 3-15. 分辨量化電壓雜訊大小分類計數結果………………… 34
圖 4-1. 電壓雜訊輸入模擬示意圖……………………………… 37
圖 4-2. 偵測能力比較統計結果………………………………… 39
圖 4-3. 本論文佈局電路圖……………………………………… 40
圖 4-4. 佈局電路搭配 5 X 1 多工器…………………………… 41
圖 4-5. 佈局電路圖加上 I/O Pad………………………………… 42
圖 4-6. 電路佈局後 DRC 結果………………………………… 43
圖 4-7. 電路佈局後 LVS 結果………………………………… 43
圖 4-8. Pre-simulation 50% VDD PSN detect result……………… 44
圖 4-9. Pre-simulation 40% VDD PSN detect result……………… 45
圖 4-10. Pre-simulation 30% VDD PSN detect result……………… 46
圖 4-11. Pre-simulation 20% VDD PSN detect result……………… 47
圖 4-12. Pre-simulation 10% VDD PSN detect result……………… 48
圖 4-13. Post-simulation 50% VDD PSN detect result…………… 49
圖 4-14. Post-simulation 40% VDD PSN detect result…………… 50
圖 4-15. Post-simulation 30% VDD PSN detect result…………… 51
圖 4-16. Post-simulation 20% VDD PSN detect result…………… 52
圖 4-17. Post-simulation 10% VDD PSN detect result…………… 53



表目錄

表 2-1. 現有技術之優缺點及改良與利用比較表……………… 20
表 3-1. 本篇論文與原始電路 MOS 數目及功率消耗比較…… 26
表 4-1. 本篇論文與原始電路偵測電壓雜訊範圍之各項比較… 36
表 4-2. 本篇論文之模擬各項電壓雜訊輸入次數……………… 38
表 4-3. 各階雜訊發生次數及 pre / post simulation 偵測率…… 54

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