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研究生:陳俊中
研究生(外文):Chun-chung Chen
論文名稱:以四埠去嵌入程序萃取金氧半場效電晶體之小訊號等效電路模型及基板參數
論文名稱(外文):Extracting MOSFET Small Signal Equivalent Circuit and Substrate Parameters with Four Port De-embedding Method
指導教授:李杰穎李杰穎引用關係
指導教授(外文):Chie-In Lee
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2009
畢業學年度:97
語文別:中文
論文頁數:77
中文關鍵詞:四埠去嵌入
外文關鍵詞:De-embedFour Port
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在電路設計上,元件的小訊號特性對於電路設計工作者而言是十分重要的。要如何去除不必要的寄生效應進而獲得本質元件的小訊號特性參數是許多研究工作者所努力的目標。
在本論文中,提出一新穎的四埠去嵌入程序,以傳統二埠串級式結構去嵌入程序為基礎,結合金屬和多晶矽接地屏蔽,將金氧半場效電晶體的四個端點分別連接至各個獨立的GSG接觸襯墊。藉由此種去嵌入程序,不但可以獲得本質元件,更能藉由利用施以不同偏壓的方式,萃取出金氧半場效電晶體的基板參數及小訊號等效電路模型。
Characteristics of small signal components for circuit designers are very important in circuit design. Many researchers have been working hard on removing the unwanted parasitic effects which is used to get the intrinsic characteristics of the small signal parameters.
In this thesis, we propose a novel four-port de-embedding procedure which based on two-port cascade structure de-embedding procedure and combined with metal and polysilicon ground-shielded technology, and let four terminals of MOSFET are connected individually to four signal pads. With such de-embedding procedure, the intrinsic and substrate element values of small-signal model are extracted by different bias.
目錄I
圖目錄II
表目錄VII
第一章 序論 1
1.1 簡介1
1.2 章節規劃2
第二章 雙埠去嵌入程序3
2.1 簡介3
2.2 一步驟去嵌入程序3
2.3 二步驟去嵌入程序6
2.4 四步驟去嵌入程序9
2.5 串級式結構去嵌入程序15
2.6 可估算去嵌入程序17
第三章 四埠去嵌入程序25
3.1 簡介25
3.2 金屬接地屏蔽技術26
3.3 多晶矽接地屏蔽技術27
3.4 結合金屬與多晶矽接地屏蔽技術28
3.5 金屬接地屏蔽與多晶矽接地屏蔽之模擬結果29
3.6 四埠可估算結合金屬和多晶矽接地屏蔽去嵌入程序33
3.7 量測結果與比較42
第四章 以四埠散射參數萃取金氧半場效電晶體基板參數53
4.1 簡介53
4.2 參數萃取54
4.3 參數萃取之結果及驗證57
第五章 結論 60
參考文獻61
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