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研究生:邱清華
研究生(外文):Ching-Hua Chiu
論文名稱:降低測試期間功率消耗為目的之掃瞄細胞排序
論文名稱(外文):Scan Cell Ordering for Power Reduction during Scan Testing
指導教授:曾王道
指導教授(外文):Wang-Dauh Tseng
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2005
畢業學年度:93
語文別:英文
論文頁數:24
中文關鍵詞:掃瞄細胞掃瞄測試掃瞄細胞排序
外文關鍵詞:scan cellscan testscan cell order
相關次數:
  • 被引用被引用:0
  • 點閱點閱:240
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  • 下載下載:8
  • 收藏至我的研究室書目清單書目收藏:0
在超大型積體電路設計中如何降低測試期間功率的消耗變得越來越重要。
尤其在掃瞄測試的架構(scan-based architecture)下,在測試資料
移位(shift)至掃瞄細胞(scan cell)期間會造成過多的功率消耗。測
試期間過多的功率消耗會導致電路成本增加以及良率的降低。因此,減
小在掃瞄測試(scan test)期間功率消耗將可以避免上述問題的產生。
本篇論文的目的就是透過去尋找對於功率消耗而言最好的掃瞄細胞排序
(scan cell order),並將掃瞄細胞以此順序串接,以降低在掃瞄測
試期間功率消耗。本篇論文中,我們使用一個轉變密度評估方程式
(induced activity function)。這個方程式可以用來測量每一個
掃瞄細胞在測試期間對受測電路造成的影響。這個方程式是以轉變密度
(transition density)作為掃瞄細胞在測試期間對受測電路影響大小
的依據。我們會使用這個函式計算每一個掃瞄細胞在測試期間對受測電
路產生的轉變密度,接著再依照這個值的大小,以由大到小的順序來串
接這些掃瞄細胞。我們也會利用在測試資料中未指定的值(unspecified
value),增加我們所提出的方法在掃瞄測試期間所能減少的功率消耗。
除此之外,當在決定掃瞄元件的串接順序過程,必須要將佈局限制(layout
constraint)同時考慮進來,佈局限制將會影響到串接的順序。因此,
我們提出一個演算法能夠在沒有違反佈局限制條件下,盡可能的以由大到
小的排列方式來串接掃瞄細胞。最後,可以由實驗結果觀察到,我們提出
的方法能夠降低在測試期間功率消耗。
Low power consumption during test application has become increasingly important in the present VLSI design. Scan-based architectures are expensive in power consumption during scanning in test vectors. Excessive power consumption during test application may result in increased product cost and decrease of overall yield. Hence, minimizing power consumption during scan test will prevent from yield loss and thus reduce product cost. The purpose of this thesis is to minimize power consumption during scan test by appropriately ordering the scan cells. In this thesis, we use an induced activity function to measure the impact of reducing the transition density at a selected pseudo input on totally switching activity in CUT. We order the scan cells in descending order according to the values of the induced activity function. We also exploit the unspecified values in the test vectors to maximize the reduction of switching activity during scan test. Besides, layout constraint is an important consideration during ordering scan cells. Hence, we develop a procedure to order scan cell without violating layout constraint. Experimental results show that the proposed approach can reduce power consumption significantly during test.
中文摘要 i
英文摘要 ii
誌謝 iii
Contents iv
List of Figures v
List of Tables vi
Chapter 1. Introduction 1
Chapter 2. Related Work 5
Chapter 3. Induced Activity Function 8
Chapter 4. Proposed Method 11
4.1. Scan cell ordering 11
4.2. Scan cell ordering under layout constraint 16
Chapter 5. Experimental Results 19
Chapter 6. Conclusions 22
References 23
[1]T. C. Huang and K. J. Lee, 「Reduction of Power Consumption in Scan-Based Circuits during Test Application by an Input Control Technique」, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, July 2001, pp.911-917.

[2]P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, 「A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation」, in Proc. 9th Great Lakes Symp. VLSI, Mar. 1999, pp.24-27.

[3]Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch, 「Power Driven Chaining of Flip-flops in Scan Architectures」, Proc. of Int』l Test Conf., 2002, pp. 796-802.

[4]O. Sinanoglu, I. Bayraktaroglu, and A. Orailoglu, 「Scan Power Reduction Through Test Data Transition Frequency Analysis」, Proc of the Int』l Test conf., 2002, pp.844-850.

[5]M. Bells, D. Bakalis and D. Nikolos, 「Scan Cell Ordering for Low Power BIST」, Proc. IEEE Computer Society Annual Symposium, Feb. 2004, pp.281-284.

[6]R.Sankaralingam, R. Oruganti, and N.A. Touba, 「Static Compaction Techniques to Control Scan Vector power Dissipation」, Proc. 18th VLSI Test Symp., IEEE CS Press, Los Alamitos, Calif., 2000, pp.35-42.

[7]R. Sankaralingam, B. Pouya, and N.A. Touba, 」Reducing Power Dissipation During Test Using Scan Chain Disable」, Proc. 19th VLSI Test Symp., IEEE CS Press, Los Alamitos, Calif., 2001, pp.319-324.

[8]Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, 「A Gated Clock Scheme for Low power Scan-Based BIST」, Proc. 7th International On-Line Testing Workshop, July 2001, pp.87-89.

[9]S. Wang and S. K. Gupta, 「DS-LFSR: A BIST TPG for Low Switching Activity」, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, July 2002, pp.842-851.

[10]S. Wang and S.K. Gupta, 「ATPG for heat Dissipation Minimization for Scan Testing」, Proc. 34th ACM/IEEE Design Auto. Cont. (DAC 97), ACM Press, New York, 1997, pp.614-619.

[11]S. Gerstendorfer and H. J .Wunderlich, 「Minimized Power Consumption for Scan-Based BIST」, Proc. of International Test Conference, pp.77-84, 1999.

[12]Y. Zorian, 「A Distributed BIST Control Scheme for Complex VLSI Devices」, 11th VLSI Test Symposium, 1993, pp.4-9.

[13]P. Girard, 「Survey of Low –Power Testing of VLSI Circuits」, IEEE Design & Test of Computer, Vol.19, May-June 2002, pp.82-92.

[14]S.Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, 」Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits」, IEEE Trans. CAD of IC & Sys., Vol.14, No.12, Dec.1995, pp.1496-1504.

[15]Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, 「Design of Routing-Constrained Low Power Scan Chains」, Proc. of the Design, Automation and Test in Europe Conference and Exhibition, 2004, pp. 62-67.
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