臺灣博碩士論文加值系統

近年來半導體產業技術不斷精進，製程也越趨於複雜並且參數也越難以控制。雖然半導體製造是在精細的加工機台及絕對潔淨的生產環境中生產，但是製程變異仍是無法避免，加上昂貴的原材料及動輒一、兩百道的製程步驟，使得在製造過程中的任何缺失或不良品的產生都會讓企業損失嚴重，因此各晶圓製造廠莫不汲於藉由各種製程控制方法或分析手法，對整個生產過程做最嚴格的控制與掌握，並將製程中可能之變異降到最低，以達到良率提升之最終目的。
然而當產品發生低良率問題時，晶圓缺陷圖樣分析是最直接及有效反應異常製程之分析，工程師往往也需要花費許多時間檢閱晶圓，找出缺陷群集的空間性特徵。但是長時間的以人工方式辨識圖樣除了會因疲勞而使得辨識正確率降低外，人為主觀判定亦會對辨識結果造成影響。因此，本研究提出二階段晶圓缺陷圖樣辨識系統，藉由此系統能夠輔助工程師快速的辨識晶圓缺陷圖樣，並對製程作最即時的反應。系統中的第一階段是利用遮罩及門檻值去除隨機性缺陷圖樣、確立系統性缺陷圖樣，以及擷取特徵值進行第二階段之類神經網路訓練，並藉由監督式學習中三種類神經網路的比較，選擇出較佳之網路結構。
在本研究中以國內某半導體廠實際之缺陷資料進行缺陷圖樣辨識，而實例驗證的結果也顯示出在本系統的第一階段中，以遮罩及門檻值的設定方式的確可以解決以往類神經網路中缺陷圖樣大小及方向性的問題，並且也可正確辨識出缺陷空間圖樣。

Nowadays, the procedures of semiconductor manufacturing have become more and more sophisticated. Though highly automated facilities are used to process the complex manufacturing steps in the near particle free environment, the yield loss is still unavoidable. Manufacturers must develop a method that enables them to improve yield. Recognizing the existence of a systematic defect provides a clue to identifying the equipment or process abnormality responsible for the defect. However, the process of defect classification is time-consuming, monotonous and costly and causes fatigue and eye-strain, which in turn cause errors in classification. For these reasons, this research intends to propose a two-phases defect pattern recognition system. The first phase is to use the masks and thresholds to eliminate the wafers with random defects and identify the existence of the systematic defects. At the same time, the features extracted from systematic defects are the inputs for constructing the neural network in the second phase. After training three supervised learning neural networks, this research compares these two neural networks by MSE of training and testing samples, and selects the better neural network.
The developed methodology is verified with industrial data from a famous semiconductor company. The existing neural-network approaches for recognizing the defect patterns on the wafer are limited by the size and the orientation of defect patterns. The experimental results demonstrate that the proposed methodology can not only solve this problem by extracting features, but also effectively identify the defect patterns on the wafer.

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