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研究生:王佑瑋
研究生(外文):Wang, Yu-Wei
論文名稱:全包覆式閘極三五族穿隧式電晶體的直徑最佳化及短通道效應之理論探討
論文名稱(外文):Theoretical Investigation of Optimized Nanowire Diameter and Short Channel Effects for Gate-All-Around III-V Tunnel FETs
指導教授:蘇彬
指導教授(外文):Su, Pin
口試委員:蘇彬趙天生林鴻志
口試委員(外文):Su, PinJhao,Tian-ShengLin, Horng-Chi
口試日期:2016-01-28
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:105
語文別:英文
論文頁數:86
中文關鍵詞:穿隧式電晶體三五族短通道效應
外文關鍵詞:III-V Tunnel FETsShort Channel Effects
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  • 下載下載:23
  • 收藏至我的研究室書目清單書目收藏:0
這篇論文藉由電腦數值模擬探討直徑對於三五族全包覆式閘極三五族穿隧式電晶體的影響。結果顯示會有最佳的直徑因為閘極控制跟量子侷限效應的互相抗衡。另外我們提出同質接面的穿隧式電晶體的模型計算跟與電腦數值模擬的互相驗證。源極跟汲極的空乏區對於穿隧式電晶體的模型計算十分重要。經由模型計算的直徑影響有著跟經由電腦數值模擬的直徑影響一樣的趨勢。最後,我們比較了穿隧式電晶體跟金氧半場效電晶體的短通道效應,並且有考慮金氧半場效電晶體的源極到汲極的穿隧電流。結果顯示金氧半場效電晶體的可伸縮性比穿隧式電晶體還要差因為隨著閘極縮短時的穿隧障礙的縮小及穿隧長度的縮小。
This thesis investigates the diameter dependence for III-V gate-all-around homojunction and heterojunction TFET using TCAD numerical simulation. The optimized diameter has been shown due to the counterbalance of the gate control and the quantum confinement effect. In addition, model calculation for the homojunction TFET is proposed and verified with TCAD numerical simulation. Source and drain depletion is very important in modeling of TFET. The diameter dependence by model calculation also shows the same trend with TCAD numerical simulation. Finally, the short channel effect of TFET has been compared with MOSFET with considering the source-to-drain tunneling current for MOSFET. Our results indicate the scalability of MOSFET is worse than TFET due to the lowering of the tunneling barrier and the tunneling length with decreasing the gate length.
摘要 i
Abstract ii
Acknowledgements iii
Related Publication iv
Contents v
Table Captions vi
Figure Captions vii
Chapter 1 Introduction 1
Chapter 2 Simulation Methodologies 5
2.1 Device Structure 5
2.2 Dynamic Nonlocal Path Band-to-Band Tunneling model in TCAD 5
2.3 Effective bandgap widening 9
2.4 Proposed Simulation Methodology 10
Chapter 3 Optimized Nanowire Diameter for III-V Homojunction and Heterojunction Gate-All-Around Tunnel FETs 28
3.1 Introduction 28
3.2 Simulation Methodologies 28
3.3 Optimized Nanowire Diameter for Homojunction TFET 29
3.4 Optimized Nanowire Diameter for Heterojunction TFET 30
3.5 Summary 31
Chapter 4 Model Calculation for III-V Homojunction Gate-All-Around Tunnel FETs 40
4.1 Introduction 40
4.2 Analytical Potential Distribution for GAA Structure Considering Source Depletion 40
4.3 Modeling of Tunneling Current 43
4.4 Model Verification and Improvement by Considering Drain Depletion 44
4.5 Summary 46
Chapter 5 Short Channel Effect of III-V Homojunction Tunnel FETs and Comparison with III-V MOSFETs 65
5.1 Introduction 65
5.2 DIBL/DIBT Comparison of Tunnel FETs and III-V MOSFETs 65
5.3 Consideration of Source-to-Drain Direct Tunneling Current for MOSFET 66
5.4 Summary 70
Chapter 6 Conclusion 81
References 83


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