臺灣博碩士論文加值系統

過去這十年，乙太網路在區域網路系統中是最成功的一種傳輸介面，而近來，億位元乙太網路已經成為最普及的區網。隨著多媒體持續發展，傳輸的資料量日益增加，在在都加速著下一代乙太網路的研發，也就是十億位元乙太網路。在下一代的系統中，數位、類比線路必須工作在125MHz，為了降低成本，傳輸的媒介乃沿用目前已經普遍架設的CAT-5網路線，同時，為了減輕類比數位轉換器的負擔以及數位信號處理的複雜度，在類比前端必須提供初步的等化補償。
在這篇論文當中，我提出了一個適用於十億位元乙太網路系統的類比前端設計，其中包含了一個零點飄移補償迴路(BLW Cancellation Loop)以及一個類比等化器。零點飄移補償迴路動態追蹤接收信號的零點，透過一個charge pump積分器將信號回授給接收信號以消去飄移信號。等化器則由一組濾波器線路所組成，透過數位振幅偵測器估計出通道長度，以切換可程式增益放大器來達成等化的效果。
這個晶片採用台積電0.35um 1P4M CMOS製程，有效面積大小為1.1 mm X 1.1mm，工作電壓為3.3V，在25pF負載電容的條件下，消耗的功率為80mW。

Ethernet has been the most successful media interface for local area networks(LANs) over the past decades. Recently, 100Mbits/s Ethernet is known as the most popular LAN. The next generation of local area networks(LANs) operates at a data rate of several hundred megabits, or gigabits per second. In order to minimize the cost, the use of the existing unshielded twisted-pair cable is desirable. However, to relax the complexity of ADC and digital signal processing circuits, the analog front end should provide coarse equalization under large echo of the copper wire.
This thesis presents the design and implementation of the front end circuits with digital control. Due to the high data rate transmission, circuits operate in tens of Mega-hertz frequency. The chip is implemented in 0.35µm 1P4M digital
CMOS technology and occupies 1.7mm X 1.7mm chip area (1.1mm X 1.1mm active) .The analog path consumes 72mW under 3.3V supply voltage with 25p load capacitance and the digital feedback path draws 2.0 mA from 3.3V supply voltage.

List of Figures iii
List of Tables v
1 Introduction 1
1.1 Present Generation LAN System . . . . . . . . . . . . . 1
1.1.1 10Base-T . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 100Base-T . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Gigabit Ethernet On Copper Wire . . . . . . . . . . . . 3
1.3 Overview of Thesis Topics . . . . . . . . . . . . . . . 3
2 Backgrounds 5
2.1 Environment of Gigabit Ethernet On Copper Wire . .. . . 5
2.2 Top Level Block Diagram . . . . . . . . . . . . . . . . 7
2.3 Channel Impairments . . . . . . . . . . . . . . . . . . 8
2.3.1 Channel Loss . . . . . . . . . . . . . . . . . .. . . 8
2.3.2 Echo . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3 Crosstalk . . . . . . . . . . . . . . . . . . . . . 10
2.4 Hybrid Architecture . . . . . . . . . . . . . . . . . 12
3 Subsystems Behavior Simulation 14
3.1 BLW Cancellation Loop . . . . . . . . . . . . . . . . 15
3.2 Analog Equalizer Loop . . . . . . . . . . . . . . . . 16
4 Subsystems Circuits Design 21
4.1 Charge Pump . . . . . . . . . . . . . . . . . . . . . 22
4.2 Summing Circuit . . . . . . . .. . . . . . . . . . . . 23
4.2.1 Linearization Techniques . . . . . . . . . . . . . . 23
4.2.2 Summing Circuit Design . . . . . . . . . . . . . . . 27
4.3 Filter Bank . . . . . . . . . . . . . . . . . . . . . 29
ii
4.3.1 Gm-C Filters . . . . . . . . . . . . . . . . . . . . 30
4.3.2 Dynamic Range . . . . . . . . . . . . . . . . . . . 33
4.3.3 Filter Bank Circuit Designs . . . . . . . . . . . . 34
4.4 Programmable Gain Amplifier . . . . . . . . . . . . . 37
4.4.1 VGA V.S. PGA . . . . . . . . . . . . . . . . . . . 37
4.4.2 PGA Circuit Design . . . . . . . . . . . . . . . . . 39
4.5 Digital Magnitude Detection . . . . . . . . . . . . . 41
5 Chip Implementation 44
5.1 Layout Design and Consideration . . . . . . . . . . . 44
5.2 Post-Layout Simulations . . . . . . . . . . . .. . . . 45
5.2.1 Summing Circuit . . . . . . . . . . . . . . . . . . 45
5.2.2 Low-Pass Filter . . . . . . . . . . . . . . . . . . 47
5.2.3 Band-Pass Filter . . . . . . . . . . . . . . . . . . 48
5.2.4 Programmable Gain Amplifier . . . . . . . . . . . .. 51
5.2.5 Charge Pump Integrator . . . . . . . . . . . . . . . 51
5.2.6 Digital Magnitude Detection . . . . . . . . . . . . 52
5.2.7 Forward Path Simulation . . . . . . . . . . . . . .. 52
6 Conclusions 57
Bibliography 58
A Pin Assignment 62
B Testing Strategies 66
C Sensitivity 69

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