臺灣博碩士論文加值系統

　　本研究提出一種數位至類比轉換器電路的架構，電路僅使用單一種低電壓源 1.8V，八位元解析度可操作在 110MHz 取樣頻率之差動式類比電壓輸出。

　　本數位至類比轉換器電路特點在於全部由 CMOS 元件所組成。無電阻、電容與電感等被動元件，也沒有二極體、雙載子電晶體等主動元件，可以以純 CMOS 邏輯製程來實現本電路，達到低製造成本目標。本電路為差動式電壓模式輸出，其具有 Class A 輸出級的特性，可直接推動 10k 歐姆的電阻並聯 10p 法拉的電容之負載。以 HSPICE 提供的指令，自行撰寫理想的類比至數位轉換器電路與理想的取樣與保持電路程式，來模擬驗證電路各項參數性能，可大幅降低電路模擬驗證時所需的複雜數位輸入訊號。本數位至類比轉換器電路大致上分為 4 個子區塊，其中包括輸入緩衝器電路、 DFF 電路、Decoder 電路與 DAC 核心電路。其中因為數位至類比轉換器電路通常會放在與數位電路非常靠近的地方，為了避免數位電路或系統以外的其它雜訊干擾，所以將數位至類比轉換器的輸出取為差動式輸出，如此可大幅降低共模雜訊的干擾，避免電路誤動作。

　　經由 HSPICE 模擬驗證且使用 TSMC 0.18um Mixed Signal SALICIDE 製程，在溫度 0℃∼70℃ 且 TT（Typical NMOS Typical PMOS）於 10kΩ 並聯 10pF 負載之下，可得最差結果（Worst Case）：上升時間為1.2ns、下降時間為1.2ns、穩定時間為6.3ns、微分非線性為0.01LSB、積分非線性為0.19LSB、突波能量為17.93pVs 與功率消耗為160mW。

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