臺灣博碩士論文加值系統

High Efficiency Video Coding (HEVC) 相較於之前的標準H.264 來說, 因為更多的預測單位大小和更多的框內預測模式種類，使得在進行框內預測來預測值的時候複雜度大幅的提升，為了減低硬體上的負擔和編碼上耗費的時間，這篇論文提出了快速演算法和設計來達到目的，我們所提出的方法包括減少預測單位大小的種類，以及減少框內預測時的預測模式來達到我們的目的。
這個方法大致上分為兩個部分，首先是對預測單元大小種類的減少，利用梯度特徵值先將預測單元大小種類減少至兩種後，再利用SATD值的分佈再將預測單元大小種類減少至一種。。第二個部分是運用一個簡單的三段式的框內預測模式選擇的演算法來對預測模式的數量來做削減。我們提出的方法在RD-rate 平均增加3.9 %, 但是相較於 HM-9.0rc的全框內編碼原始設定來說大約節省79 %的編碼時間。
在硬體的部分我們為RMD 處理程序設計了新的排程，。RMD 部分的硬體若以TSMC 90nm的技術合成，大約需要224.6K邏輯閘的數目量及1.762K位元組的晶片內建記憶體，而其可在工作頻率為270MHz的情況下，滿足處理畫面大小為4K×2K，每秒30張畫面的影片規格。

When compared to previous video standard H.264, High Efficiency Video Coding (HEVC) has significant computation complexity because of more PU size types and more intra prediction modes. To achieve real time encoding demands, this paper proposes a fast intra prediction algorithm and its design.
The fast algorithm can be divided into two parts. The first part is the fast intra prediction unit (PU) size selection that is a gradient weight controlled block size selection to reduce PU sizes to two. These two PU sizes will be reduced to one for more complexity reduction based on the SATD distribution. The required intra prediction modes are reduced by almost half by s simple three-step algorithm. The simulation results show that the proposed algorithm can save 79% encoding time on average for all-intra main case compared to the default encoding scheme in HM-9.0rc1, with 3.9% BD-rate increases
With TSMC 90 nm CMOS technology and 270 MHz operating frequency, the gate count of this work is about 224.608K and the memory usage is 1.762 Kbytes to support the 4k×2k 30 fps video encoding.

Contents
Contents IV
List of Figures VI
List of Tables VIII
Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2. Overview of HEVC Standard 3
2.1 Overview of HEVC 3
2.2 Coding Structure in HEVC 5
2.3 Intra Prediction in HEVC 7
2.4 Challenges in HEVC Implementation 12
Chapter 3. Proposed Fast Intra Prediction Algorithm 14
3.1 Introduction of Related Work 14
3.2 Fast Intra Block Size Selection Algorithm 16
3.2.1 Analysis of Skipping Intra Block Size 16
3.2.2 Illustration for used features 20
3.2.3 Fast Intra Block Size Selection Algorithm 31
3.3 Fast Intra Mode Selection Algorithm 64
3.4 Overall Fast Intra Prediction Algorithm 70
3.5 Summary 72
Chapter 4. Hardware Design for HEVC Encoder 73
4.1 System Analysis 73
4.2 Overall Encoder Architecture 75
4.3 RMD Stage Scheduling and Architecture 76
4.4 Synthesis Results 82
4.5 Summary 84
Chapter 5. Conclusion and Future Work 85
5.1 Conclusion 85
5.2 Future work 86
Appendix A . Introduction to AdaBoost Algorithm 87
A.1 Machine Learning Methods 87
A.2 AdaBoost Algorithm 88
A.3 AdaBoost Model Use Example 90
Appendix B . AdaBoost Model 93
Reference 99

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