臺灣博碩士論文加值系統

本文設計一個新式6位元的快閃類比數位轉換器，使用Threshold Invert Quantization(TIQ)技術的比較器來取代傳統OPAMP的比較器架構，並且設計新型的TIQ比較器架構，限制TIQ比較器轉態時的電流，有效地降低整體電路的功率消耗。
使用HSPICE及TSMC 0.35μm製程的模擬，供應電壓為3.3 V。對於6位元TIQ 快閃類比數位轉換器的模擬結果如下：微分非線性誤差(DNL)為+0.13 LSB至-0.17 LSB，積分非線性誤差(INL)為+0.15 LSB至-0.07 LSB。當取樣頻率為400 MHz，輸入頻率為1 MHz至100 MHz時，消耗功率為24 mW至37 mW，而傳統TIQ電路功率消耗為41 mW至644 mW。在輸入1 MHz的正弦波時，訊號對雜訊與失真比(SNDR)為35.21db，有效位元(ENOB)為5.55位元。
TIQ比較器的Flash-ADC有許多優點：較簡單的比較器電路架構、比較速度快、電路中不需要電阻串、TIQ比較器中不需要時脈訊號或耦合電容、適合標準CMOS的技術以及SOC的整合

In this thesis, we design a new 6-Bit flash analog to digital converter. It uses the Threshold Invert Quantization (TIQ) technology to replace traditional OPAMP comparator architecture to design a new TIQ comparator architecture, and it limits the current of the TIQ comparator when it is under transition. It could effectively reduce the overall circuit power consumption.

The function and performance of the circuit was simulated by HSPICE utilizing TSMC 0.35 μm CMOS HSPICE model, and the power supply voltage is 3.3V. The 6-Bit TIQ flash analog to digital converter simulation results are as follows: DNL is +0.13 LSB to -0.07 LSB, INL is +0.15 LSB to -0.07 LSB. And the results show that when the sampling frequency is at 400 MHz, and the input frequency varies from 1 MHz to 100 MHz, the power consumption varies from 24 mW to 37 mW, while the power consumption of traditional TIQ flash-ADC are 41 mW to 644 mW. When input is a 1MHz sine wave signal, SNDR is 35.21dB and ENOB is 5.55 Bit.

TIQ comparator Flash-ADC has many advantages: simple comparator circuit architecture, relatively fast, the circuit does not require resistor string, TIQ comparator does not require a clock signal or the coupling capacitor, suitable for standard CMOS technology and SOC integration

TABLE OF CONTENTS
摘要•••••••••••••••••••••••••Ⅰ
Abstract ••••••••••••••••••••Ⅱ
誌謝•••••••••••••••••••••••••Ⅲ
LIST OF FIGURES•••••••••••••Ⅵ
LIST OF TABLES••••••••••••••Ⅷ

Chapter 1 Introduction •••••••••••••••••••••••••••••1
1-1 Motivation•••••••••••••••••••••••••••••••1
1-2 Organization for the thesis••••••••••••••2
Chapter 2 Fundamentals of ADC•••••••••••••3
2-1 Introduction•••••••••••••••3
2-2 Flash ADC••••••••••••••••3
2-3 Two-step ADC••••••••••••••••••5
2-4 Interpolating ADC•••••••••••••••6
2-5 Folding ADC•••••••••••••7
2-6 Pipelined ADC••••••••••••••8
2-7 Specification••••••••••••••••9
2-7-1 Least significant Bit (LSB) •••••••••••••9
2-7-2 Differential nonlinearity (DNL) •••••••••9
2-7-3 Integral nonlinearity (INL) ••••••••••10
2-7-4 Sample rate••••••••••••••••••11
2-7-5 Signal to noise ratio (SNR) •••••••••••11
2-7-6 Signal to noise and distortion ratio (SNDR) ••••12
2-7-7 Effective number of Bits (ENOB) •••••••••12
Chapter 3 Circuit Design and Analysis•••••••••••••13
3-1 Introduction•••••••••••••••••••••••••13
3-2 TIQ Flash-ADC Architecture••••••••••••••13
3-3 Traditional TIQ comparator•••••••••••14
3-4 New TIQ comparator••••••••••••••••••17
3-5 Latch•••••••••••••••••••••••••20
3-6 Encoder•••••••••••••••••••••••21
Chapter 4 Simulation Result•••••••••••••••••••••22
4-1 Pre-simulation••••••••••••••••22
4-2 Post-simulation•••••••••••••••••••27
Chapter 5 Conclusion•••••••••••••••••••••••••••••31
References•••••••••••••••••••••••••••••••••••••32
作者簡歷••••••••••••••••••••••••••35
LIST OF FIGURES
Fig. 2-1 Traditional flash-ADC••••••••••••••••••••4
Fig. 2-2 Two-step ADC•••••••••••••••••••••••••••••5
Fig. 2-3 Interpolating ADC••••••••••••••••••••••••••••••6
Fig. 2-4 Folding ADC••••••••••••••••••••••••••••••••7
Fig. 2-5 Pipelined ADC••••••••••••••••••••••••••••••8
Fig. 2-6 DNL••••••••••••••••••••••••••••••••••10
Fig. 2-7 INL•••••••••••••••••••••••••••••••••11
Fig. 3-1 TIQ Flash-ADC•••••••••••••••••••••••••••14
Fig. 3-2 Threshold voltages of each comparators••••••••15
Fig. 3-3 Traditional TIQ comparator••••••••••••••••16
Fig. 3-4 Converted curve of traditional TIQ comparator••••••16
Fig. 3-5 New TIQ comparator•••••••••••••••••18
Fig. 3-6 Current curve of two kinds TIQ comparator••••••••••19
Fig. 3-7 Latch circuit•••••••••••••••••••••20
Fig. 3-8 ROM based encoder••••••••••••••••••21
Fig. 4-1 6-BIT of flash-ADC•••••••••••••••••••22
Fig. 4-2 The DNL of proposed flash-ADC••••••••••••23
Fig. 4-3 The INL of proposed flash-ADC••••••••••••••••23
Fig. 4-4 The post simulation results of the proposed ADC with a ramp input •••••••••••••••••••••27
Fig. 4-5 DNL of proposed ADC•••••••••••••••••••27
Fig. 4-6 INL of proposed ADC•••••••••••••28
Fig. 4-7 SNDR of proposed ADC••••••••••••••••••28
Fig. 4-8 Layout of flash-ADC••••••••••••••••••••••29

LIST OF TABLES
Table 4-1 ENOB of different sample frequency•••••••••••24
Table 4-2 ENOB of different temperature••••••••••••••••24
Table 4-3 Traditional TIQ Flash-ADC vs New TIQ Flash-ADC•••••••25
Table 4-4 Pre simulation vs post simulation ••••••••30

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