臺灣博碩士論文加值系統

由於骨牌邏輯電路通常較互補式金氧半元件電路計具有較小的面積與更快的速度，所以已經被廣泛使用於高速處理器的設計中。近年來雖許多關於高速混合式靜態/動態電路的研究然而大部份的研究卻忽略探討如何實現其研究成果。在本篇論文中，我們嘗試針對混合式結和式的靜態/動態電路，去建立一個使用標準元件的自動化設計流程(Cell-Based Design Flow)，包含了時序歪斜容忍(Skew Tolerant)及低功率(Low Power)與高效能(High Performance)等特性，並且完成實際晶片的實作與驗證。我們在這個研究上達成了三個主要目標：首先，我們提供了一個靜態-動態-靜態(Static-Dynamic-Static, SDS)高效率且低功率的混合結合式靜態/動態電路設計技術；第二點，我們以提供了可支援自動電路合成的設計流成，在這方面，我們重點放在克服使用現行的CAD工具會產生時序歪斜的問題；最後，我們也設計動態電路元件庫具有處理電荷分享(Charge Sharing)與串音干擾(Cross-Talk)的雜訊減輕(Noise-Alleviation)問題的能力，供標準元件設計合成的自動化CAD工具使用。
關鍵字：混合/結合，靜態電路，動態電路，標準元件庫

Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design high-performance processors. There are several research works on high-performance mixed static/dynamic circuit; but most of the works focus on the theory discussion without practical results are presented. In this thesis we try to establish the cell based design flow of the mixed/merged static/dynamic circuit synthesis, which has skew tolerant, low-power and high-performance characteristics. And, the real chip implementation and silicon proven will be validated finally. In this work, there is three major targets are got: Target-one, we propose a static-dynamic-static(SDS)high-performance/low-power mixed/merged static/dynamic circuit design techniques. Target-two: the supported synthesizable design flow has been established for Target-one; we focus on the skew-tolerant issue of this target by using current CAD tools. Target-three, two noise-alleviation (charge sharing, crosstalk) domino cell libraries are generated to support the cell-based synthesis CAD design tools.
Key word：mixed/merged，static circuit，dynamic circuit，cell base

封面內頁
簽名頁
授權書 iii
中文摘要 iv
英文摘要 v
誌謝 vi
目錄 vii
圖目錄 x
表目錄 xiii

第一章 序論 1
1.1 研究動機 1
1.2 論文研究方向 1
1.3 論文研究重點 3
1.4 章節安排 5
第二章 相關背景研究 6
2.1 相關論文研究 6
2.2 動態電路簡述與問題說明 9
2.2.1 電荷分享(Charge Sharing) 10
2.2.2 漏電流(Leakage Current) 11
2.2.3 資料競走(Internal Race) 12
2.3 骨牌式邏輯電路 13
第三章 靜動態混合電路 15
3.1 電路設計 15
3.2 靜/動/靜態混合電路 16
3.3 找出電路中的切點(cut point) 18
3.4 電路切割 21
3.5 找出電路DS切點 23
第四章 設計流程 26
4.1 設計流程 26
4.2 前段程序 28
4.2.1 前段程序-domino flow 29
4.2.2 前段程序- SD flow 32
4.2.3 前段程序- DS flow 33
4.3 後段程序 34
4.3.1 標準元件庫建立 35
4.3.2 參數萃取 38
4.4 驗證程序 40
4.4.1 形式驗証 40
4.4.2 測試向量驗證 41
4.4.3 Fault coverage analysis 43
第五章 實驗結果分析 46
5.1 組合電路延遲量測方式 46
5.2 循序電路延遲量測方式 48
5.3 Synopsys數據量測 50
5.4 Verilog XL 延遲量測 52
5.5 NANOSIM 量測 54
5.6 元件參數萃取誤差驗證 55
第六章 結論 57
參考文獻 58

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